| Line 76... |
Line 76... |
`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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// Parity error indicator
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p_err,
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`endif
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// SPRs
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// SPRs
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spr_cs, spr_write, spr_dat_i, spr_addr, mtspr_dc_done
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spr_cs, spr_write, spr_dat_i, spr_addr, mtspr_dc_done
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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| Line 135... |
Line 140... |
input mbist_si_i;
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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output mbist_so_o;
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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output [1:0] p_err;
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`endif
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//
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//
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// SPR access
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// SPR access
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//
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//
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input spr_cs;
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input spr_cs;
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input spr_write;
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input spr_write;
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| Line 166... |
Line 175... |
assign dcqmem_rty_o = ~dcqmem_ack_o;
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assign dcqmem_rty_o = ~dcqmem_ack_o;
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assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
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assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
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assign mtspr_dc_done = 1'b1;
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assign mtspr_dc_done = 1'b1;
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`ifdef OR1200_RAM_PARITY
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assign p_err = 0;
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`endif
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`else
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`else
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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| Line 183... |
Line 196... |
wire [31:0] dc_addr;
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wire [31:0] dc_addr;
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wire dcfsm_biu_read;
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wire dcfsm_biu_read;
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wire dcfsm_biu_write;
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wire dcfsm_biu_write;
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wire dcfsm_dcram_di_sel;
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wire dcfsm_dcram_di_sel;
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wire dcfsm_biu_do_sel;
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wire dcfsm_biu_do_sel;
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reg tagcomp_miss;
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wire tagcomp_miss;
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wire [`OR1200_DCINDXH:`OR1200_DCLS] dctag_addr;
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wire [`OR1200_DCINDXH:`OR1200_DCLS] dctag_addr;
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wire dctag_en;
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wire dctag_en;
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wire dctag_v;
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wire dctag_v;
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wire dctag_dirty;
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wire dctag_dirty;
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| Line 211... |
Line 224... |
wire mbist_ram_si = mbist_si_i;
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wire mbist_ram_si = mbist_si_i;
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wire mbist_tag_si = mbist_ram_so;
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wire mbist_tag_si = mbist_ram_so;
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assign mbist_so_o = mbist_tag_so;
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assign mbist_so_o = mbist_tag_so;
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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wire [1:0] p_err_wire;
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// Indicate an error if we're reading from the RAM (hit)
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// Additionally, mask with tag_v as tag ram is properly cleared during
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// init, whereas the data RAM is not.
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assign p_err[0] = (dcqmem_ack_o & (!dcfsm_first_miss_ack | dc_en) &
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!dcqmem_we_i) &
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(tag_v & !p_err[1]) ? p_err_wire[0] : 0;
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// Whenever there's a tag parity error and we have an instruction fetch
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assign p_err[1] = (dctag_en & !dctag_we) ? p_err_wire[1] : 0;
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`endif
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// Address out to external bus - always from FSM
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// Address out to external bus - always from FSM
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assign dcsb_adr_o = dc_addr;
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assign dcsb_adr_o = dc_addr;
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//
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//
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// SPR register decodes
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// SPR register decodes
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//
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//
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| Line 288... |
Line 316... |
//
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//
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// Tag comparison
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// Tag comparison
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//
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//
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wire [31:`OR1200_DCTAGL] dcqmem_adr_i_tag;
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wire [31:`OR1200_DCTAGL] dcqmem_adr_i_tag;
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assign dcqmem_adr_i_tag = dcqmem_adr_i[31:`OR1200_DCTAGL];
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assign dcqmem_adr_i_tag = dcqmem_adr_i[31:`OR1200_DCTAGL];
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/*
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always @(tag or dcqmem_adr_i_tag or tag_v) begin
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always @(tag or dcqmem_adr_i_tag or tag_v) begin
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if ((tag != dcqmem_adr_i_tag) || !tag_v)
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if ((tag != dcqmem_adr_i_tag) || !tag_v
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tagcomp_miss = 1'b1;
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`ifdef OR1200_RAM_PARITY
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else
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| p_err
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tagcomp_miss = 1'b0;
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`endif
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end
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)
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tagcomp_miss = 1'b1;
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else
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tagcomp_miss = 1'b0;
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end
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*/
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assign tagcomp_miss = (tag != dcqmem_adr_i_tag) | !tag_v
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`ifdef OR1200_RAM_PARITY
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| (|p_err_wire)
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`endif
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;
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//
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//
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// Instantiation of DC Finite State Machine
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// Instantiation of DC Finite State Machine
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//
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//
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or1200_dc_fsm or1200_dc_fsm(
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or1200_dc_fsm or1200_dc_fsm(
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.clk(clk),
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.clk(clk),
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| Line 347... |
Line 384... |
// RAM BIST
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// RAM BIST
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.mbist_si_i(mbist_ram_si),
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.mbist_si_i(mbist_ram_si),
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.mbist_so_o(mbist_ram_so),
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.mbist_so_o(mbist_ram_so),
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.mbist_ctrl_i(mbist_ctrl_i),
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.mbist_ctrl_i(mbist_ctrl_i),
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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.p_err(p_err_wire[0]),
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`endif
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.addr(dc_addr[`OR1200_DCINDXH:2]),
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.addr(dc_addr[`OR1200_DCINDXH:2]),
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.en(dc_en),
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.en(dc_en),
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.we(dcram_we),
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.we(dcram_we),
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.datain(to_dcram),
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.datain(to_dcram),
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.dataout(from_dcram)
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.dataout(from_dcram)
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| Line 366... |
Line 406... |
// RAM BIST
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// RAM BIST
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.mbist_si_i(mbist_tag_si),
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.mbist_si_i(mbist_tag_si),
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.mbist_so_o(mbist_tag_so),
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.mbist_so_o(mbist_tag_so),
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.mbist_ctrl_i(mbist_ctrl_i),
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.mbist_ctrl_i(mbist_ctrl_i),
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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.p_err(p_err_wire[1]),
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`endif
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.addr(dctag_addr),
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.addr(dctag_addr),
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.en(dctag_en),
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.en(dctag_en),
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.we(dctag_we),
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.we(dctag_we),
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.datain({dc_addr[31:`OR1200_DCTAGL], dctag_v, dctag_dirty}),
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.datain({dc_addr[31:`OR1200_DCTAGL], dctag_v, dctag_dirty}),
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.tag_v(tag_v),
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.tag_v(tag_v),
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