URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dmmu_tlb.v] - Diff between revs 360 and 482

Rev 360	Rev 482
Line 241...	Line 241...
`.ce(tlb_mr_en),`	`.ce(tlb_mr_en),`
`.we(tlb_mr_we),`	`.we(tlb_mr_we),`
`.addr(tlb_index),`	`.addr(tlb_index),`
`.di(tlb_mr_ram_in),`	`.di(tlb_mr_ram_in),`
`.doq(tlb_mr_ram_out)`	`.doq(tlb_mr_ram_out)`
	`ifdef OR1200_RAM_PARITY
	`, .p_err()`
	`endif
`);`	`);`

`//`	`//`
`// Instantiation of DTLB Translate Registers`	`// Instantiation of DTLB Translate Registers`
`//`	`//`
Line 266...	Line 269...
`.ce(tlb_tr_en),`	`.ce(tlb_tr_en),`
`.we(tlb_tr_we),`	`.we(tlb_tr_we),`
`.addr(tlb_index),`	`.addr(tlb_index),`
`.di(tlb_tr_ram_in),`	`.di(tlb_tr_ram_in),`
`.doq(tlb_tr_ram_out)`	`.doq(tlb_tr_ram_out)`
	`ifdef OR1200_RAM_PARITY
	`, .p_err()`
	`endif
`);`	`);`

`endmodule // or1200_dmmu_tlb`	`endmodule // or1200_dmmu_tlb`

`No newline at end of file`	`No newline at end of file`