| Line 67... |
Line 67... |
`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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`endif
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|
|
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`ifdef OR1200_RAM_PARITY
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// Parity error indicator
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p_err,
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`endif
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// SPR access
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// SPR access
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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);
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);
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|
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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| Line 106... |
Line 111... |
input mbist_si_i;
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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output mbist_so_o;
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`endif
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`endif
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|
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`ifdef OR1200_RAM_PARITY
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output [1:0] p_err;
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`endif
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//
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//
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// SPR access
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// SPR access
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//
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//
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input spr_cs;
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input spr_cs;
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input spr_write;
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input spr_write;
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| Line 124... |
Line 133... |
wire v;
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wire v;
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wire [`OR1200_DTLB_INDXW-1:0] tlb_index;
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wire [`OR1200_DTLB_INDXW-1:0] tlb_index;
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wire tlb_mr_en;
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wire tlb_mr_en;
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wire tlb_mr_we;
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wire tlb_mr_we;
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wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_in;
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wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_in;
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`ifdef OR1200_RAM_PARITY
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wire [`OR1200_DTLBMRW-1+2:0] tlb_mr_ram_out;
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`else
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wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_out;
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wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_out;
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`endif
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wire tlb_tr_en;
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wire tlb_tr_en;
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wire tlb_tr_we;
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wire tlb_tr_we;
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wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_in;
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wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_in;
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wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_out;
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wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_out;
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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| Line 140... |
Line 153... |
wire mbist_mr_si = mbist_si_i;
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wire mbist_mr_si = mbist_si_i;
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wire mbist_tr_si = mbist_mr_so;
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wire mbist_tr_si = mbist_mr_so;
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assign mbist_so_o = mbist_tr_so;
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assign mbist_so_o = mbist_tr_so;
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`endif
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`endif
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|
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`ifdef OR1200_RAM_PARITY
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wire [1:0] p_err_wire;
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reg p_err_en;
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`endif
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//
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//
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// Implemented bits inside match and translate registers
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// Implemented bits inside match and translate registers
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//
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//
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// dtlbwYmrX: vpn 31-19 v 0
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// dtlbwYmrX: vpn 31-19 v 0
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// dtlbwYtrX: ppn 31-13 swe 9 sre 8 uwe 7 ure 6
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// dtlbwYtrX: ppn 31-13 swe 9 sre 8 uwe 7 ure 6
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| Line 185... |
Line 203... |
32'h00000000;
|
32'h00000000;
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|
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//
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//
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// Assign outputs from Match registers
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// Assign outputs from Match registers
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//
|
//
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assign {vpn, v} = tlb_mr_ram_out;
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assign {vpn, v} = tlb_mr_ram_out[`OR1200_DTLBMRW-1:0];
|
|
|
//
|
//
|
// Assign to Match registers inputs
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// Assign to Match registers inputs
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//
|
//
|
assign tlb_mr_ram_in = {spr_dat_i[`OR1200_DTLB_TAG], spr_dat_i[`OR1200_DTLBMR_V_BITS]};
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assign tlb_mr_ram_in = {spr_dat_i[`OR1200_DTLB_TAG], spr_dat_i[`OR1200_DTLBMR_V_BITS]};
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| Line 210... |
Line 228... |
spr_dat_i[`OR1200_DTLBTR_CI_BITS]};
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spr_dat_i[`OR1200_DTLBTR_CI_BITS]};
|
|
|
//
|
//
|
// Generate hit
|
// Generate hit
|
//
|
//
|
assign hit = (vpn == vaddr[`OR1200_DTLB_TAG]) & v;
|
assign hit = (vpn == vaddr[`OR1200_DTLB_TAG]) & v
|
|
`ifdef OR1200_RAM_PARITY
|
|
& !p_err
|
|
`endif
|
|
;
|
|
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//
|
//
|
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
|
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
|
// spr_addr[5:0].
|
// spr_addr[5:0].
|
//
|
//
|
assign tlb_index = spr_cs ? spr_addr[`OR1200_DTLB_INDXW-1:0] : vaddr[`OR1200_DTLB_INDX];
|
assign tlb_index = spr_cs ? spr_addr[`OR1200_DTLB_INDXW-1:0] :
|
|
vaddr[`OR1200_DTLB_INDX];
|
|
|
|
`ifdef OR1200_RAM_PARITY
|
|
always @(posedge clk)
|
|
if (rst)
|
|
p_err_en <= 0;
|
|
else
|
|
p_err_en <= (tlb_mr_en & !tlb_mr_we) | (tlb_tr_en & !tlb_tr_we);
|
|
|
|
assign p_err = (p_err_en & (tlb_mr_en & !tlb_mr_we) |
|
|
(tlb_tr_en & !tlb_tr_we)) ? p_err_wire : 0;
|
|
`endif
|
|
|
|
|
//
|
//
|
// Instantiation of DTLB Match Registers
|
// Instantiation of DTLB Match Registers
|
//
|
//
|
//or1200_spram_64x14 dtlb_mr_ram(
|
//or1200_spram_64x14 dtlb_mr_ram(
|
or1200_spram #
|
or1200_spram #
|
(
|
(
|
.aw(6),
|
.aw(6),
|
|
`ifdef OR1200_RAM_PARITY
|
|
.dw(16)
|
|
`else
|
.dw(14)
|
.dw(14)
|
|
`endif
|
)
|
)
|
dtlb_ram
|
dtlb_mr_ram
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
|
.rst(rst),
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
.mbist_si_i(mbist_mr_si),
|
.mbist_si_i(mbist_mr_si),
|
.mbist_so_o(mbist_mr_so),
|
.mbist_so_o(mbist_mr_so),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
`endif
|
`endif
|
.ce(tlb_mr_en),
|
.ce(tlb_mr_en),
|
.we(tlb_mr_we),
|
.we(tlb_mr_we),
|
.addr(tlb_index),
|
.addr(tlb_index),
|
.di(tlb_mr_ram_in),
|
|
.doq(tlb_mr_ram_out)
|
|
`ifdef OR1200_RAM_PARITY
|
`ifdef OR1200_RAM_PARITY
|
, .p_err()
|
.p_err(p_err_wire[0]),
|
|
.di({2'b00,tlb_mr_ram_in}),
|
|
`else
|
|
.di(tlb_mr_ram_in),
|
`endif
|
`endif
|
|
.doq(tlb_mr_ram_out)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of DTLB Translate Registers
|
// Instantiation of DTLB Translate Registers
|
//
|
//
|
//or1200_spram_64x24 dtlb_tr_ram(
|
|
or1200_spram #
|
or1200_spram #
|
(
|
(
|
.aw(6),
|
.aw(6),
|
.dw(24)
|
.dw(24)
|
)
|
)
|
dtlb_tr_ram
|
dtlb_tr_ram
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
|
.rst(rst),
|
`ifdef OR1200_BIST
|
`ifdef OR1200_BIST
|
// RAM BIST
|
// RAM BIST
|
.mbist_si_i(mbist_tr_si),
|
.mbist_si_i(mbist_tr_si),
|
.mbist_so_o(mbist_tr_so),
|
.mbist_so_o(mbist_tr_so),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
`endif
|
`endif
|
|
`ifdef OR1200_RAM_PARITY
|
|
.p_err(p_err_wire[1]),
|
|
`endif
|
.ce(tlb_tr_en),
|
.ce(tlb_tr_en),
|
.we(tlb_tr_we),
|
.we(tlb_tr_we),
|
.addr(tlb_index),
|
.addr(tlb_index),
|
.di(tlb_tr_ram_in),
|
.di(tlb_tr_ram_in),
|
.doq(tlb_tr_ram_out)
|
.doq(tlb_tr_ram_out)
|
`ifdef OR1200_RAM_PARITY
|
|
, .p_err()
|
|
`endif
|
|
);
|
);
|
|
|
endmodule // or1200_dmmu_tlb
|
endmodule // or1200_dmmu_tlb
|
|
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No newline at end of file
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No newline at end of file
|
