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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_dpram
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module or1200_dpram
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(
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(
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rst,
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// Generic synchronous double-port RAM interface
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// Generic synchronous double-port RAM interface
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clk_a, ce_a, addr_a, do_a,
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clk_a, ce_a, addr_a, do_a,
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clk_b, ce_b, we_b, addr_b, di_b
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clk_b, ce_b, we_b, addr_b, di_b
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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, p_err
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, p_err
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parameter dw = 32;
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parameter dw = 32;
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//
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//
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// Generic synchronous double-port RAM interface
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// Generic synchronous double-port RAM interface
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//
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//
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input rst; // Reset
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input clk_a; // Clock
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input clk_a; // Clock
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input ce_a; // Chip enable input
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input ce_a; // Chip enable input
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input [aw-1:0] addr_a; // address bus inputs
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input [aw-1:0] addr_a; // address bus inputs
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output [dw-1:0] do_a; // output data bus
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output [dw-1:0] do_a; // output data bus
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input clk_b; // Clock
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input clk_b; // Clock
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//
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//
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// Generic RAM's registers and wires
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// Generic RAM's registers and wires
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//
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//
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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reg [(dw+(dw/8))-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/; // RAM content
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parameter par_w = (dw/8);
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reg [(dw+par_w)-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/; // RAM content
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`else
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`else
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reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/; // RAM content
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reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/; // RAM content
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`endif
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`endif
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reg [aw-1:0] addr_a_reg; // RAM address registered
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reg [aw-1:0] addr_a_reg; // RAM address registered
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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wire [(dw+(dw/8))-1:0] do_a_wire;
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wire [(dw+par_w)-1:0] do_a_wire;
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wire [(dw/8)-1:0] di_p;
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wire [par_w-1:0] di_p;
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wire [(dw/8)-1:0] do_p;
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wire [par_w-1:0] do_p;
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wire [(dw/8)-1:0] parity_err;
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wire [par_w-1:0] parity_err;
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`else
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`else
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wire [dw-1:0] do_a_wire;
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wire [dw-1:0] do_a_wire;
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`endif
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`endif
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// Function to access GPRs (for use by Verilator). No need to hide this one
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// Function to access GPRs (for use by Verilator). No need to hide this one
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// from the simulator, since it has an input (as required by IEEE 1364-2001).
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// from the simulator, since it has an input (as required by IEEE 1364-2001).
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function [31:0] get_gpr;
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function [31:0] get_gpr;
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// verilator public
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// verilator public
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input [aw-1:0] gpr_no;
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input [aw-1:0] gpr_no;
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reg [(dw+(dw/8))-1:0] gpr_temp;
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begin
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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reg [(dw+par_w)-1:0] gpr_temp;
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begin
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gpr_temp = mem[gpr_no];
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gpr_temp = mem[gpr_no];
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get_gpr = gpr_temp[31:0];
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get_gpr = gpr_temp[31:0];
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end
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`else
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`else
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get_gpr = mem[gpr_no];
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get_gpr = mem[gpr_no];
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`endif
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`endif
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end
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endfunction // get_gpr
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endfunction // get_gpr
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task set_gpr;
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task set_gpr;
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// verilator public
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// verilator public
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input [aw-1:0] gpr_no;
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input [aw-1:0] gpr_no;
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endtask // get_gpr
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endtask // get_gpr
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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genvar i;
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genvar i;
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generate
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generate
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for (i=0;i<(dw/8);i=i+1) begin: paritygen
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for (i=0;i<par_w;i=i+1) begin: paritygen
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or1200_parity_gen pgen(.d_i(di_b[(i*8)+7:(i*8)]), .p_o(di_p[i]));
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or1200_parity_gen pgen(.d_i(di_b[(i*8)+7:(i*8)]), .p_o(di_p[i]));
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or1200_parity_chk pchk(.d_i(do_a_wire[(i*8)+7:(i*8)]),
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or1200_parity_chk pchk(.d_i(do_a_wire[(i*8)+7:(i*8)]),
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.p_i(do_p[i]), .err_o(parity_err[i]));
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.p_i(do_p[i]), .err_o(parity_err[i]));
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end
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end
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endgenerate
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endgenerate
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// Extract parity bits of data out
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// Extract parity bits of data out
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assign do_p = do_a_wire[(dw+(dw/8))-1:dw];
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assign do_p = do_a_wire[(dw+par_w)-1:dw];
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reg ce_a_r;
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always @(posedge clk_a)
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if (rst)
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ce_a_r <= 0;
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else
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ce_a_r <= ce_a;
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// Indicate error
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// Indicate error
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assign p_err = (|parity_err);
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assign p_err = (|parity_err) & ce_a_r;
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// Inject a parity error. Can specify GPR number to affect,
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// Inject a parity error. Can specify GPR number to affect,
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// and which parity or data bit to switch.
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// and which parity or data bit to switch.
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task gen_parity_err;
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task gen_parity_err;
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input [aw-1:0] gpr_no;
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input [aw-1:0] gpr_no;
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input [31:0] parity_bit_no;
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input [31:0] parity_bit_no;
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input [31:0] data_bit_no;
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input [31:0] data_bit_no;
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reg [(dw+(dw/8))-1:0] do_temp;
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reg [(dw+par_w)-1:0] do_temp;
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begin
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begin
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do_temp = mem[gpr_no];
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do_temp = mem[gpr_no];
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// Switch parity bit
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// Switch parity bit
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if (parity_bit_no > 0)
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if (parity_bit_no >= 0 && parity_bit_no < par_w)
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do_temp[dw+(parity_bit_no-1)] = ~do_temp[dw+(parity_bit_no-1)];
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do_temp[dw+parity_bit_no] = ~do_temp[dw+parity_bit_no];
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// Switch data bit
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// Switch data bit
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if (data_bit_no > 0 && data_bit_no <= dw)
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if (data_bit_no >= 0 && data_bit_no < dw)
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do_temp[data_bit_no-1] = ~do_temp[data_bit_no-1];
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do_temp[data_bit_no] = ~do_temp[data_bit_no];
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// Write word back
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// Write word back
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mem[gpr_no] = do_temp;
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mem[gpr_no] = do_temp;
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end
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end
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endtask // gen_parity_err
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endtask // gen_parity_err
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`endif
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`endif
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//
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//
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// Data output drivers
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// Data output drivers
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//
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//
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