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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_du.v] - Diff between revs 363 and 815

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Rev 363 Rev 815
Line 410... Line 410...
                                dcr6_sel,
                                dcr6_sel,
                                dcr7_sel;       // DCR selects
                                dcr7_sel;       // DCR selects
wire                            dwcr0_sel,
wire                            dwcr0_sel,
                                dwcr1_sel;      // DWCR selects
                                dwcr1_sel;      // DWCR selects
reg                             dbg_bp_r;
reg                             dbg_bp_r;
 
reg                             ex_freeze_q;
`ifdef OR1200_DU_HWBKPTS
`ifdef OR1200_DU_HWBKPTS
reg     [31:0]                   match_cond0_ct;
reg     [31:0]                   match_cond0_ct;
reg     [31:0]                   match_cond1_ct;
reg     [31:0]                   match_cond1_ct;
reg     [31:0]                   match_cond2_ct;
reg     [31:0]                   match_cond2_ct;
reg     [31:0]                   match_cond3_ct;
reg     [31:0]                   match_cond3_ct;
Line 527... Line 528...
`endif
`endif
`ifdef OR1200_DU_DWCR1
`ifdef OR1200_DU_DWCR1
assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
`endif
`endif
 
 
 
// Track previous ex_freeze to detect when signals are updated
 
always @(posedge clk)
 
  ex_freeze_q <= ex_freeze;
 
 
//
//
// Decode started exception
// Decode started exception
//
//
// du_except_stop comes from or1200_except
// du_except_stop comes from or1200_except
//   
//   
always @(du_except_stop) begin
always @(du_except_stop or ex_freeze_q) begin
        except_stop = 14'b00_0000_0000_0000;
        except_stop = 14'b00_0000_0000_0000;
        casez (du_except_stop)
        casez (du_except_stop)
                14'b1?_????_????_????:
                14'b1?_????_????_????:
                        except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
                        except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
                14'b01_????_????_????: begin
                14'b01_????_????_????: begin
Line 564... Line 569...
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
                14'b00_0000_0000_1???: begin
                14'b00_0000_0000_1???: begin
                        except_stop[`OR1200_DU_DRR_RE] = 1'b1;
                        except_stop[`OR1200_DU_DRR_RE] = 1'b1;
                end
                end
                14'b00_0000_0000_01??: begin
                14'b00_0000_0000_01??: begin
                        except_stop[`OR1200_DU_DRR_TE] = 1'b1;
                        except_stop[`OR1200_DU_DRR_TE] = 1'b1 & ~ex_freeze_q;
                end
                end
                14'b00_0000_0000_001?: begin
                14'b00_0000_0000_001?: begin
                        except_stop[`OR1200_DU_DRR_FPE] = 1'b1;
                        except_stop[`OR1200_DU_DRR_FPE] = 1'b1;
                end
                end
                14'b00_0000_0000_0001:
                14'b00_0000_0000_0001:
                        except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
                        except_stop[`OR1200_DU_DRR_SCE] = 1'b1 & ~ex_freeze_q;
                default:
                default:
                        except_stop = 14'b00_0000_0000_0000;
                        except_stop = 14'b00_0000_0000_0000;
        endcase
        endcase // casez (du_except_stop)
end
end
 
 
//
//
// dbg_bp_o is registered
// dbg_bp_o is registered
//
//

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