Subversion Repositories openrisc

reg     [2:0]                    delayed_iee;

reg     [2:0]                    delayed_iee;

reg     [2:0]                    delayed_tee;

reg     [2:0]                    delayed_tee;

wire                            int_pending;

wire                            int_pending;

wire                            tick_pending;

wire                            tick_pending;

wire                            fp_pending;

wire                            fp_pending;

reg trace_trap      ;

reg trace_trap      ;

reg ex_freeze_prev;

reg ex_freeze_prev;

reg sr_ted_prev;

reg sr_ted_prev;

reg dsr_te_prev;

reg dsr_te_prev;

                      & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]);

                      & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]);

assign fp_pending = sig_fp & fpcsr_fpee & ~ex_freeze & ~ex_branch_taken

assign fp_pending = sig_fp & fpcsr_fpee & ~ex_freeze & ~ex_branch_taken

                    & ~ex_dslot;

                    & ~ex_dslot;

// Abort write into RF by load & other instructions   

// Abort write into RF by load & other instructions   

assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align |

assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align |

                  sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val

                  sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val

                                 & !sr_ted & !dsr_te);

                                 & !sr_ted & !dsr_te);

                      sig_dtlbmiss      & ~du_dsr[`OR1200_DU_DSR_DME],

                      sig_dtlbmiss      & ~du_dsr[`OR1200_DU_DSR_DME],

                      sig_trap          & ~du_dsr[`OR1200_DU_DSR_TE],

                      sig_trap          & ~du_dsr[`OR1200_DU_DSR_TE],

                      sig_syscall       & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,

                      sig_syscall       & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,

                      sig_dmmufault     & ~du_dsr[`OR1200_DU_DSR_DPFE],

                      sig_dmmufault     & ~du_dsr[`OR1200_DU_DSR_DPFE],

                      sig_dbuserr       & ~du_dsr[`OR1200_DU_DSR_BUSEE],

                      sig_dbuserr       & ~du_dsr[`OR1200_DU_DSR_BUSEE],

                      fp_pending        & ~du_dsr[`OR1200_DU_DSR_FPE],

                      fp_pending        & ~du_dsr[`OR1200_DU_DSR_FPE],

                      int_pending       & ~du_dsr[`OR1200_DU_DSR_IE],

                      int_pending       & ~du_dsr[`OR1200_DU_DSR_IE],

                      tick_pending      & ~du_dsr[`OR1200_DU_DSR_TTE]

                      tick_pending      & ~du_dsr[`OR1200_DU_DSR_TTE]

                      };

                      };

                        sig_illegal             & du_dsr[`OR1200_DU_DSR_IIE],

                        sig_illegal             & du_dsr[`OR1200_DU_DSR_IIE],

                        sig_align               & du_dsr[`OR1200_DU_DSR_AE],

                        sig_align               & du_dsr[`OR1200_DU_DSR_AE],

                        sig_dtlbmiss            & du_dsr[`OR1200_DU_DSR_DME],

                        sig_dtlbmiss            & du_dsr[`OR1200_DU_DSR_DME],

                        sig_dmmufault           & du_dsr[`OR1200_DU_DSR_DPFE],

                        sig_dmmufault           & du_dsr[`OR1200_DU_DSR_DPFE],

                        sig_dbuserr             & du_dsr[`OR1200_DU_DSR_BUSEE],

                        sig_dbuserr             & du_dsr[`OR1200_DU_DSR_BUSEE],

                        sig_trap                & du_dsr[`OR1200_DU_DSR_TE],

                        sig_trap                & du_dsr[`OR1200_DU_DSR_TE],

                        fp_pending              & du_dsr[`OR1200_DU_DSR_FPE],

                        fp_pending              & du_dsr[`OR1200_DU_DSR_FPE],

                        sig_syscall             & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze

                        sig_syscall             & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze

                };

                };