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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's Exception logic ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// Description ////
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//// Handles all OR1K exceptions inside CPU block. ////
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//// ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Log: or1200_except.v,v $
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//
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Structure reordered and bugs fixed.
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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`define OR1200_EXCEPTFSM_WIDTH 3
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`define OR1200_EXCEPTFSM_IDLE `OR1200_EXCEPTFSM_WIDTH'd0
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`define OR1200_EXCEPTFSM_FLU1 `OR1200_EXCEPTFSM_WIDTH'd1
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`define OR1200_EXCEPTFSM_FLU2 `OR1200_EXCEPTFSM_WIDTH'd2
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`define OR1200_EXCEPTFSM_FLU3 `OR1200_EXCEPTFSM_WIDTH'd3
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`define OR1200_EXCEPTFSM_FLU4 `OR1200_EXCEPTFSM_WIDTH'd4
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`define OR1200_EXCEPTFSM_FLU5 `OR1200_EXCEPTFSM_WIDTH'd5
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//
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// Exception recognition and sequencing
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//
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module or1200_except
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(
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// Clock and reset
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clk, rst,
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// Internal i/f
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sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss,
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sig_dmmufault, sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault,
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sig_tick, ex_branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze,
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if_stall, if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe,
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extend_flush, except_flushpipe, except_type, except_start, except_started,
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except_stop, except_trig, ex_void, abort_mvspr, branch_op, spr_dat_ppc,
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spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, esr, sr_we, to_sr, sr, lsu_addr,
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abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, sig_fp, fpcsr_fpee
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);
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//
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// I/O
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//
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input clk;
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input rst;
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input sig_ibuserr;
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input sig_dbuserr;
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input sig_illegal;
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input sig_align;
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input sig_range;
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input sig_dtlbmiss;
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input sig_dmmufault;
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input sig_int;
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input sig_syscall;
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input sig_trap;
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input sig_itlbmiss;
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input sig_immufault;
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input sig_tick;
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input sig_fp;
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input fpcsr_fpee;
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input ex_branch_taken;
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input genpc_freeze;
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input id_freeze;
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input ex_freeze;
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input wb_freeze;
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input if_stall;
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input [31:0] if_pc;
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output [31:0] id_pc;
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output [31:0] ex_pc;
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output [31:0] wb_pc;
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input [31:0] datain;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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input [24:0] du_dmr1;
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input du_hwbkpt;
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input du_hwbkpt_ls_r;
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input epcr_we;
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input eear_we;
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input esr_we;
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input pc_we;
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output [31:0] epcr;
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output [31:0] eear;
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output [`OR1200_SR_WIDTH-1:0] esr;
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input [`OR1200_SR_WIDTH-1:0] to_sr;
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input sr_we;
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input [`OR1200_SR_WIDTH-1:0] sr;
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input [31:0] lsu_addr;
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input id_flushpipe;
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input ex_flushpipe;
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output except_flushpipe;
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output extend_flush;
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output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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output except_start;
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output except_started;
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output [13:0] except_stop;
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output [13:0] except_trig;
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input ex_void;
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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output [31:0] spr_dat_ppc;
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output [31:0] spr_dat_npc;
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output abort_ex;
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output abort_mvspr;
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input icpu_ack_i;
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input icpu_err_i;
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input dcpu_ack_i;
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input dcpu_err_i;
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//
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// Internal regs and wires
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//
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reg [`OR1200_EXCEPT_WIDTH-1:0] except_type /* verilator public */;
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reg [31:0] id_pc /* verilator public */;
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reg id_pc_val;
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reg [31:0] ex_pc /* verilator public */;
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reg ex_pc_val;
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reg [31:0] wb_pc /* verilator public */;
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reg [31:0] dl_pc;
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reg [31:0] epcr;
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reg [31:0] eear;
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reg [`OR1200_SR_WIDTH-1:0] esr;
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reg [2:0] id_exceptflags;
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reg [2:0] ex_exceptflags;
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reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
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reg extend_flush;
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reg extend_flush_last;
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reg ex_dslot /* verilator public */;
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reg delayed1_ex_dslot;
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reg delayed2_ex_dslot;
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wire except_started;
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wire except_flushpipe /* verilator public */;
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reg [2:0] delayed_iee;
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reg [2:0] delayed_tee;
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wire int_pending;
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wire tick_pending;
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wire fp_pending;
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reg trace_trap ;
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reg ex_freeze_prev;
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reg sr_ted_prev;
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reg dsr_te_prev;
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reg dmr1_st_prev ;
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reg dmr1_bt_prev ;
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wire dsr_te = ex_freeze_prev ? dsr_te_prev : du_dsr[`OR1200_DU_DSR_TE];
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wire sr_ted = ex_freeze_prev ? sr_ted_prev : sr[`OR1200_SR_TED];
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wire dmr1_st = ex_freeze_prev ? dmr1_st_prev: du_dmr1[`OR1200_DU_DMR1_ST] ;
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wire dmr1_bt = ex_freeze_prev ? dmr1_bt_prev: du_dmr1[`OR1200_DU_DMR1_BT] ;
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//
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// Simple combinatorial logic
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//
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assign except_started = extend_flush & except_start;
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assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
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assign int_pending = sig_int & (sr[`OR1200_SR_IEE] |
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(sr_we & to_sr[`OR1200_SR_IEE]))
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& id_pc_val & delayed_iee[2] & ~ex_freeze & ~ex_branch_taken
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& ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_IEE]);
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assign tick_pending = sig_tick & (sr[`OR1200_SR_TEE] |
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(sr_we & to_sr[`OR1200_SR_TEE])) & id_pc_val
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& delayed_tee[2] & ~ex_freeze & ~ex_branch_taken
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& ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]);
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assign fp_pending = sig_fp & fpcsr_fpee & ~ex_freeze & ~ex_branch_taken
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& ~ex_dslot;
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// Abort write into RF by load & other instructions
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assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align |
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sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val
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& !sr_ted & !dsr_te);
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// abort spr read/writes
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assign abort_mvspr = sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val
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& !sr_ted & !dsr_te) ;
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assign spr_dat_ppc = wb_pc;
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assign spr_dat_npc = ex_void ? id_pc : ex_pc;
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//
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// Order defines exception detection priority
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//
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assign except_trig = {
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ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
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sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
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sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
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sig_trap & ~du_dsr[`OR1200_DU_DSR_TE],
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sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
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sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
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fp_pending & ~du_dsr[`OR1200_DU_DSR_FPE],
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int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
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tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE]
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};
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wire trace_cond = !ex_freeze && !ex_void && (1'b0
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`ifdef OR1200_DU_DMR1_ST
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|| dmr1_st
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`endif
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`ifdef OR1200_DU_DMR1_BT
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|| ((branch_op != `OR1200_BRANCHOP_NOP) && (branch_op != `OR1200_BRANCHOP_RFE) && dmr1_bt)
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`endif
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);
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assign except_stop = {
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tick_pending & du_dsr[`OR1200_DU_DSR_TTE],
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int_pending & du_dsr[`OR1200_DU_DSR_IE],
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ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
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sig_align & du_dsr[`OR1200_DU_DSR_AE],
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sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
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sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_range & du_dsr[`OR1200_DU_DSR_RE],
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sig_trap & du_dsr[`OR1200_DU_DSR_TE],
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fp_pending & du_dsr[`OR1200_DU_DSR_FPE],
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sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
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};
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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if (rst == `OR1200_RST_VALUE) begin
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trace_trap <= 1'b0 ;
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end
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else if (!(trace_trap && !ex_pc_val)) begin
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trace_trap <= trace_cond & !dsr_te & !sr_ted ;
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end
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end
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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if (rst == `OR1200_RST_VALUE) begin
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ex_freeze_prev <= 1'b0 ;
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sr_ted_prev <= 1'b0 ;
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dsr_te_prev <= 1'b0 ;
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dmr1_st_prev <= 1'b0 ;
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dmr1_bt_prev <= 1'b0 ;
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end
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else begin
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ex_freeze_prev <= ex_freeze ;
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if (!ex_freeze_prev || ex_void) begin
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sr_ted_prev <= sr [`OR1200_SR_TED ] ;
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dsr_te_prev <= du_dsr [`OR1200_DU_DSR_TE ] ;
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dmr1_st_prev <= du_dmr1[`OR1200_DU_DMR1_ST] ;
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dmr1_bt_prev <= du_dmr1[`OR1200_DU_DMR1_BT] ;
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end
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end
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end
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`ifdef verilator
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// Function to access wb_pc (for Verilator). Have to hide this from
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// simulator, since functions with no inputs are not allowed in IEEE
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// 1364-2001.
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function [31:0] get_wb_pc;
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// verilator public
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get_wb_pc = wb_pc;
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endfunction // get_wb_pc
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// Function to access id_pc (for Verilator). Have to hide this from
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// simulator, since functions with no inputs are not allowed in IEEE
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// 1364-2001.
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function [31:0] get_id_pc;
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// verilator public
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get_id_pc = id_pc;
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endfunction // get_id_pc
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// Function to access ex_pc (for Verilator). Have to hide this from
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// simulator, since functions with no inputs are not allowed in IEEE
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// 1364-2001.
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function [31:0] get_ex_pc;
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// verilator public
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get_ex_pc = ex_pc;
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endfunction // get_ex_pc
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// Function to access except_type[3:0] (for Verilator). Have to hide this from
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// simulator, since functions with no inputs are not allowed in IEEE
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// 1364-2001.
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function [3:0] get_except_type;
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// verilator public
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get_except_type = except_type;
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endfunction // get_except_type
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`endif
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//
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// PC and Exception flags pipelines
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//
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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if (rst == `OR1200_RST_VALUE) begin
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id_pc <= 32'd0;
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id_pc_val <= 1'b0 ;
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id_exceptflags <= 3'b000;
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end
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else if (id_flushpipe) begin
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id_pc_val <= 1'b0 ;
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id_exceptflags <= 3'b000;
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end
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else if (!id_freeze) begin
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id_pc <= if_pc;
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id_pc_val <= 1'b1 ;
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id_exceptflags <= { sig_ibuserr, sig_itlbmiss, sig_immufault };
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end
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end
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//
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// delayed_iee
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//
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// SR[IEE] should not enable interrupts right away
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// when it is restored with l.rfe. Instead delayed_iee
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// together with SR[IEE] enables interrupts once
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// pipeline is again ready.
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//
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always @(`OR1200_RST_EVENT rst or posedge clk)
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if (rst == `OR1200_RST_VALUE)
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delayed_iee <= 3'b000;
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else if (!sr[`OR1200_SR_IEE])
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delayed_iee <= 3'b000;
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else
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delayed_iee <= {delayed_iee[1:0], 1'b1};
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//
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// delayed_tee
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//
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// SR[TEE] should not enable tick exceptions right away
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// when it is restored with l.rfe. Instead delayed_tee
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// together with SR[TEE] enables tick exceptions once
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// pipeline is again ready.
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//
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always @(`OR1200_RST_EVENT rst or posedge clk)
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if (rst == `OR1200_RST_VALUE)
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delayed_tee <= 3'b000;
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else if (!sr[`OR1200_SR_TEE])
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delayed_tee <= 3'b000;
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else
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delayed_tee <= {delayed_tee[1:0], 1'b1};
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//
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// PC and Exception flags pipelines
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//
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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if (rst == `OR1200_RST_VALUE) begin
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ex_dslot <= 1'b0;
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ex_pc <= 32'd0;
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ex_pc_val <= 1'b0 ;
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ex_exceptflags <= 3'b000;
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delayed1_ex_dslot <= 1'b0;
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delayed2_ex_dslot <= 1'b0;
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end
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else if (ex_flushpipe) begin
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ex_dslot <= 1'b0;
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ex_pc_val <= 1'b0 ;
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ex_exceptflags <= 3'b000;
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delayed1_ex_dslot <= 1'b0;
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delayed2_ex_dslot <= 1'b0;
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end
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else if (!ex_freeze & id_freeze) begin
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ex_dslot <= 1'b0;
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ex_pc <= id_pc;
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ex_pc_val <= id_pc_val ;
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ex_exceptflags <= 3'b000;
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delayed1_ex_dslot <= ex_dslot;
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delayed2_ex_dslot <= delayed1_ex_dslot;
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end
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else if (!ex_freeze) begin
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ex_dslot <= ex_branch_taken;
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ex_pc <= id_pc;
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ex_pc_val <= id_pc_val ;
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ex_exceptflags <= id_exceptflags;
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delayed1_ex_dslot <= ex_dslot;
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delayed2_ex_dslot <= delayed1_ex_dslot;
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end
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end
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//
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// PC and Exception flags pipelines
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//
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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if (rst == `OR1200_RST_VALUE) begin
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wb_pc <= 32'd0;
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dl_pc <= 32'd0;
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end
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else if (!wb_freeze) begin
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wb_pc <= ex_pc;
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dl_pc <= wb_pc;
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end
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end
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//
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// We have started execution of exception handler:
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// 1. Asserted for 3 clock cycles
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// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler
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//
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assign except_flushpipe = |except_trig & ~|state;
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//
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// Exception FSM that sequences execution of exception handler
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//
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// except_type signals which exception handler we start fetching in:
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// 1. Asserted in next clock cycle after exception is recognized
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//
|
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
|
if (rst == `OR1200_RST_VALUE) begin
|
|
state <= `OR1200_EXCEPTFSM_IDLE;
|
|
except_type <= `OR1200_EXCEPT_NONE;
|
|
extend_flush <= 1'b0;
|
|
epcr <= 32'b0;
|
|
eear <= 32'b0;
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|
esr <= {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
|
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extend_flush_last <= 1'b0;
|
|
end
|
|
else begin
|
|
`ifdef OR1200_CASE_DEFAULT
|
|
case (state) // synopsys parallel_case
|
|
`else
|
|
case (state) // synopsys full_case parallel_case
|
|
`endif
|
|
`OR1200_EXCEPTFSM_IDLE:
|
|
if (except_flushpipe) begin
|
|
state <= `OR1200_EXCEPTFSM_FLU1;
|
|
extend_flush <= 1'b1;
|
|
esr <= sr_we ? to_sr : sr;
|
|
casex (except_trig)
|
|
`ifdef OR1200_EXCEPT_ITLBMISS
|
|
14'b1x_xxxx_xxxx_xxxx: begin
|
|
except_type <= `OR1200_EXCEPT_ITLBMISS;
|
|
eear <= ex_dslot ?
|
|
ex_pc : ex_pc;
|
|
epcr <= ex_dslot ?
|
|
wb_pc : ex_pc;
|
|
end
|
|
`endif
|
|
`ifdef OR1200_EXCEPT_IPF
|
|
14'b01_xxxx_xxxx_xxxx: begin
|
|
except_type <= `OR1200_EXCEPT_IPF;
|
|
eear <= ex_dslot ?
|
|
ex_pc : delayed1_ex_dslot ?
|
|
id_pc : delayed2_ex_dslot ?
|
|
id_pc : id_pc;
|
|
epcr <= ex_dslot ?
|
|
wb_pc : delayed1_ex_dslot ?
|
|
id_pc : delayed2_ex_dslot ?
|
|
id_pc : id_pc;
|
|
end
|
|
`endif
|
|
`ifdef OR1200_EXCEPT_BUSERR
|
|
14'b00_1xxx_xxxx_xxxx: begin // Insn. Bus Error
|
|
except_type <= `OR1200_EXCEPT_BUSERR;
|
|
eear <= ex_dslot ?
|
|
wb_pc : ex_pc;
|
|
epcr <= ex_dslot ?
|
|
wb_pc : ex_pc;
|
|
end
|
|
`endif
|
|
`ifdef OR1200_EXCEPT_ILLEGAL
|
|
14'b00_01xx_xxxx_xxxx: begin
|
|
except_type <= `OR1200_EXCEPT_ILLEGAL;
|
|
eear <= ex_pc;
|
|
epcr <= ex_dslot ?
|
|
wb_pc : ex_pc;
|
|
end
|
|
`endif
|
|
`ifdef OR1200_EXCEPT_ALIGN
|
|
14'b00_001x_xxxx_xxxx: begin
|
|
except_type <= `OR1200_EXCEPT_ALIGN;
|
|
eear <= lsu_addr;
|
|
epcr <= ex_dslot ?
|
|
wb_pc : ex_pc;
|
|
end
|
|
`endif
|
|
`ifdef OR1200_EXCEPT_DTLBMISS
|
|
14'b00_0001_xxxx_xxxx: begin
|
|
except_type <= `OR1200_EXCEPT_DTLBMISS;
|
|
eear <= lsu_addr;
|
|
epcr <= ex_dslot ?
|
|
wb_pc : delayed1_ex_dslot ?
|
|
dl_pc : ex_pc;
|
|
end
|
|
`endif
|
|
`ifdef OR1200_EXCEPT_TRAP
|
|
14'b00_0000_1xxx_xxxx: begin
|
|
except_type <= `OR1200_EXCEPT_TRAP;
|
|
epcr <= ex_dslot ?
|
|
wb_pc : delayed1_ex_dslot ?
|
|
id_pc : ex_pc;
|
|
end
|
|
`endif
|
|
`ifdef OR1200_EXCEPT_SYSCALL
|
|
14'b00_0000_01xx_xxxx: begin
|
|
except_type <= `OR1200_EXCEPT_SYSCALL;
|
|
epcr <= ex_dslot ?
|
|
wb_pc : delayed1_ex_dslot ?
|
|
id_pc : delayed2_ex_dslot ?
|
|
id_pc : id_pc;
|
|
end
|
|
`endif
|
|
`ifdef OR1200_EXCEPT_DPF
|
|
14'b00_0000_001x_xxxx: begin
|
|
except_type <= `OR1200_EXCEPT_DPF;
|
|
eear <= lsu_addr;
|
|
epcr <= ex_dslot ?
|
|
wb_pc : delayed1_ex_dslot ?
|
|
dl_pc : ex_pc;
|
|
end
|
|
`endif
|
|
`ifdef OR1200_EXCEPT_BUSERR
|
|
14'b00_0000_0001_xxxx: begin // Data Bus Error
|
|
except_type <= `OR1200_EXCEPT_BUSERR;
|
|
eear <= lsu_addr;
|
|
epcr <= ex_dslot ?
|
|
wb_pc : delayed1_ex_dslot ?
|
|
dl_pc : ex_pc;
|
|
end
|
|
`endif
|
|
`ifdef OR1200_EXCEPT_RANGE
|
|
14'b00_0000_0000_1xxx: begin
|
|
except_type <= `OR1200_EXCEPT_RANGE;
|
|
epcr <= ex_dslot ?
|
|
wb_pc : delayed1_ex_dslot ?
|
|
id_pc : delayed2_ex_dslot ?
|
|
id_pc : id_pc;
|
|
end
|
|
`endif
|
|
`ifdef OR1200_EXCEPT_FLOAT
|
|
14'b00_0000_0000_01xx: begin
|
|
except_type <= `OR1200_EXCEPT_FLOAT;
|
|
epcr <= id_pc;
|
|
end
|
|
`endif
|
|
`ifdef OR1200_EXCEPT_INT
|
|
14'b00_0000_0000_001x: begin
|
|
except_type <= `OR1200_EXCEPT_INT;
|
|
epcr <= id_pc;
|
|
end
|
|
`endif
|
|
`ifdef OR1200_EXCEPT_TICK
|
|
14'b00_0000_0000_0001: begin
|
|
except_type <= `OR1200_EXCEPT_TICK;
|
|
epcr <= id_pc;
|
|
end
|
|
`endif
|
|
default:
|
|
except_type <= `OR1200_EXCEPT_NONE;
|
|
endcase
|
|
end
|
|
else if (pc_we) begin
|
|
state <= `OR1200_EXCEPTFSM_FLU1;
|
|
extend_flush <= 1'b1;
|
|
end
|
|
else begin
|
|
if (epcr_we)
|
|
epcr <= datain;
|
|
if (eear_we)
|
|
eear <= datain;
|
|
if (esr_we)
|
|
esr <= {datain[`OR1200_SR_WIDTH-1], 1'b1, datain[`OR1200_SR_WIDTH-3:0]};
|
|
end
|
|
`OR1200_EXCEPTFSM_FLU1:
|
|
if (icpu_ack_i | icpu_err_i | genpc_freeze)
|
|
state <= `OR1200_EXCEPTFSM_FLU2;
|
|
`OR1200_EXCEPTFSM_FLU2:
|
|
`ifdef OR1200_EXCEPT_TRAP
|
|
if (except_type == `OR1200_EXCEPT_TRAP) begin
|
|
state <= `OR1200_EXCEPTFSM_IDLE;
|
|
extend_flush <= 1'b0;
|
|
extend_flush_last <= 1'b0;
|
|
except_type <= `OR1200_EXCEPT_NONE;
|
|
end
|
|
else
|
|
`endif
|
|
state <= `OR1200_EXCEPTFSM_FLU3;
|
|
`OR1200_EXCEPTFSM_FLU3:
|
|
begin
|
|
state <= `OR1200_EXCEPTFSM_FLU4;
|
|
end
|
|
`OR1200_EXCEPTFSM_FLU4: begin
|
|
state <= `OR1200_EXCEPTFSM_FLU5;
|
|
extend_flush <= 1'b0;
|
|
extend_flush_last <= 1'b0; // damjan
|
|
end
|
|
`ifdef OR1200_CASE_DEFAULT
|
|
default: begin
|
|
`else
|
|
`OR1200_EXCEPTFSM_FLU5: begin
|
|
`endif
|
|
if (!if_stall && !id_freeze) begin
|
|
state <= `OR1200_EXCEPTFSM_IDLE;
|
|
except_type <= `OR1200_EXCEPT_NONE;
|
|
extend_flush_last <= 1'b0;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
