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/////////////////////////////////////////////////////////////////////
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//// ////
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//// or1200_fpu_intfloat_conv ////
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//// Only conversion between 32-bit integer and single ////
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//// precision floating point format ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// Modified by Julius Baxter, July, 2010 ////
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//// julius.baxter@orsoc.se ////
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//// ////
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//// TODO: Fix bug where 1.0f in round up goes to integer 2 ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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/*
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FPU Operations (fpu_op):
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========================
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0 =
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1 =
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2 =
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3 =
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4 = int to float
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5 = float to int
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6 =
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7 =
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Rounding Modes (rmode):
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=======================
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0 = round_nearest_even
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1 = round_to_zero
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2 = round_up
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3 = round_down
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*/
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module or1200_fpu_intfloat_conv
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(
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clk, rmode, fpu_op, opa, out, snan, ine, inv,
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overflow, underflow, zero
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);
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input clk;
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input [1:0] rmode;
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input [2:0] fpu_op;
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input [31:0] opa;
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output [31:0] out;
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output snan;
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output ine;
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output inv;
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output overflow;
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output underflow;
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output zero;
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parameter INF = 31'h7f800000,
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QNAN = 31'h7fc00001,
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SNAN = 31'h7f800001;
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////////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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reg zero;
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reg [31:0] opa_r; // Input operand registers
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reg [31:0] out; // Output register
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reg div_by_zero; // Divide by zero output register
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wire [7:0] exp_fasu; // Exponent output from EQU block
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reg [7:0] exp_r; // Exponent output (registerd)
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wire co; // carry output
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wire [30:0] out_d; // Intermediate final result output
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wire overflow_d, underflow_d;// Overflow/Underflow
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reg inf, snan, qnan;// Output Registers for INF, S/QNAN
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reg ine; // Output Registers for INE
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reg [1:0] rmode_r1, rmode_r2,// Pipeline registers for round mode
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rmode_r3;
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reg [2:0] fpu_op_r1, fpu_op_r2,// Pipeline registers for fp
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// operation
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fpu_op_r3;
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////////////////////////////////////////////////////////////////////////
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//
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// Input Registers
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//
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always @(posedge clk)
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opa_r <= opa;
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always @(posedge clk)
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rmode_r1 <= rmode;
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always @(posedge clk)
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rmode_r2 <= rmode_r1;
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always @(posedge clk)
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rmode_r3 <= rmode_r2;
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always @(posedge clk)
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fpu_op_r1 <= fpu_op;
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always @(posedge clk)
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fpu_op_r2 <= fpu_op_r1;
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always @(posedge clk)
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fpu_op_r3 <= fpu_op_r2;
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////////////////////////////////////////////////////////////////////////
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//
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// Exceptions block
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//
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wire inf_d, ind_d, qnan_d, snan_d, opa_nan;
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wire opa_00;
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wire opa_inf;
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wire opa_dn;
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or1200_fpu_intfloat_conv_except u0
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( .clk(clk),
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.opa(opa_r),
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.opb(),
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.inf(inf_d),
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.ind(ind_d),
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.qnan(qnan_d),
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.snan(snan_d),
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.opa_nan(opa_nan),
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.opb_nan(),
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.opa_00(opa_00),
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.opb_00(),
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.opa_inf(opa_inf),
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.opb_inf(),
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.opa_dn(opa_dn),
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.opb_dn()
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);
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////////////////////////////////////////////////////////////////////////
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//
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// Pre-Normalize block
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// - Adjusts the numbers to equal exponents and sorts them
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// - determine result sign
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// - determine actual operation to perform (add or sub)
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//
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wire nan_sign_d, result_zero_sign_d;
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reg sign_fasu_r;
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wire [1:0] exp_ovf;
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reg [1:0] exp_ovf_r;
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// This is all we need from post-norm module for int-float conversion
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reg opa_sign_r;
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always @(posedge clk)
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opa_sign_r <= opa_r[31];
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always @(posedge clk)
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sign_fasu_r <= opa_sign_r; //sign_fasu;
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////////////////////////////////////////////////////////////////////////
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//
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// Normalize Result
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//
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wire ine_d;
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wire inv_d;
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wire sign_d;
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reg sign;
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reg [30:0] opa_r1;
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reg [47:0] fract_i2f;
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reg opas_r1, opas_r2;
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wire f2i_out_sign;
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wire [47:0] fract_denorm;
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always @(posedge clk) // Exponent must be once cycle delayed
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case(fpu_op_r2)
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//4: exp_r <= 0;
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5: exp_r <= opa_r1[30:23];
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default: exp_r <= 0;
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endcase
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always @(posedge clk)
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opa_r1 <= opa_r[30:0];
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always @(posedge clk)
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fract_i2f <= (fpu_op_r2==5) ?
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(sign_d ? 1-{24'h00, (|opa_r1[30:23]), opa_r1[22:0]}-1 :
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{24'h0, (|opa_r1[30:23]), opa_r1[22:0]})
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: (sign_d ? 1 - {opa_r1, 17'h01} : {opa_r1, 17'h0});
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assign fract_denorm = fract_i2f;
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always @(posedge clk)
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opas_r1 <= opa_r[31];
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always @(posedge clk)
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opas_r2 <= opas_r1;
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assign sign_d = opa_sign_r; //sign_fasu;
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always @(posedge clk)
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sign <= (rmode_r2==2'h3) ? !sign_d : sign_d;
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// Special case of largest negative integer we can convert to - usually
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// gets picked up as invalid, but really it's not, so deal with it as a
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// special case.
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wire f2i_special_case_no_inv;
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assign f2i_special_case_no_inv = (opa == 32'hcf000000);
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or1200_fpu_post_norm_intfloat_conv u4
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(
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.clk(clk), // System Clock
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.fpu_op(fpu_op_r3), // Floating Point Operation
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.opas(opas_r2), // OPA Sign
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.sign(sign), // Sign of the result
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.rmode(rmode_r3), // Rounding mode
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.fract_in(fract_denorm), // Fraction Input
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.exp_in(exp_r), // Exponent Input
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.opa_dn(opa_dn), // Operand A Denormalized
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.opa_nan(opa_nan),
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.opa_inf(opa_inf),
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.opb_dn(), // Operand B Denormalized
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.out(out_d), // Normalized output (un-registered)
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.ine(ine_d), // Result Inexact output (un-registered)
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.inv(inv_d), // Invalid input for f2i operation
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.overflow(overflow_d), // Overflow output (un-registered)
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.underflow(underflow_d),// Underflow output (un-registered)
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.f2i_out_sign(f2i_out_sign) // F2I Output Sign
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);
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////////////////////////////////////////////////////////////////////////
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//
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// FPU Outputs
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//
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reg fasu_op_r1, fasu_op_r2;
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wire [30:0] out_fixed;
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wire output_zero_fasu;
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wire overflow_fasu;
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wire out_d_00;
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wire ine_fasu;
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wire underflow_fasu;
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/*
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always @(posedge clk)
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fasu_op_r1 <= fasu_op;
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always @(posedge clk)
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fasu_op_r2 <= fasu_op_r1;
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*/
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// Force pre-set values for non numerical output
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assign out_fixed = ( (qnan_d | snan_d) |
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(ind_d /*& !fasu_op_r2*/)) ? QNAN : INF;
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always @(posedge clk)
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out[30:0] <= /*((inf_d & (fpu_op_r3!=3'b101)) | snan_d | qnan_d)
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& fpu_op_r3!=3'b100 ? out_fixed :*/ out_d;
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assign out_d_00 = !(|out_d);
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always @(posedge clk)
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out[31] <= (fpu_op_r3==3'b101) ?
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f2i_out_sign : sign_fasu_r;
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// Exception Outputs
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assign ine_fasu = (ine_d | overflow_d | underflow_d) &
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!(snan_d | qnan_d | inf_d);
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always @(posedge clk)
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ine <= fpu_op_r3[2] ? ine_d : ine_fasu;
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assign overflow = overflow_d & !(snan_d | qnan_d | inf_d);
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assign underflow = underflow_d & !(inf_d | snan_d | qnan_d);
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always @(posedge clk)
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snan <= snan_d & (fpu_op_r3==3'b101); // Only signal sNaN when ftoi
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// Status Outputs
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assign output_zero_fasu = out_d_00 & !(inf_d | snan_d | qnan_d);
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always @(posedge clk)
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zero <= fpu_op_r3==3'b101 ? out_d_00 & !(snan_d | qnan_d) :
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output_zero_fasu ;
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assign inv = inv_d & !f2i_special_case_no_inv;
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endmodule // or1200_fpu_intfloat_conv
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module or1200_fpu_intfloat_conv_except
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(
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clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan,
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opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn
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);
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input clk;
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input [31:0] opa, opb;
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output inf, ind, qnan, snan, opa_nan, opb_nan;
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output opa_00, opb_00;
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output opa_inf, opb_inf;
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output opa_dn;
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output opb_dn;
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////////////////////////////////////////////////////////////////////////
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//
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// Local Wires and registers
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//
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wire [7:0] expa, expb; // alias to opX exponent
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wire [22:0] fracta, fractb; // alias to opX fraction
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reg expa_ff, infa_f_r, qnan_r_a, snan_r_a;
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reg expb_ff, infb_f_r, qnan_r_b, snan_r_b;
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reg inf, ind, qnan, snan; // Output registers
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reg opa_nan, opb_nan;
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reg expa_00, expb_00, fracta_00, fractb_00;
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reg opa_00, opb_00;
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reg opa_inf, opb_inf;
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reg opa_dn, opb_dn;
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////////////////////////////////////////////////////////////////////////
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//
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// Aliases
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//
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assign expa = opa[30:23];
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assign expb = opb[30:23];
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assign fracta = opa[22:0];
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assign fractb = opb[22:0];
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////////////////////////////////////////////////////////////////////////
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//
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// Determine if any of the input operators is a INF or NAN or any other
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// special number
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//
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always @(posedge clk)
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expa_ff <= &expa;
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always @(posedge clk)
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expb_ff <= &expb;
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always @(posedge clk)
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infa_f_r <= !(|fracta);
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always @(posedge clk)
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infb_f_r <= !(|fractb);
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always @(posedge clk)
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qnan_r_a <= fracta[22];
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always @(posedge clk)
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snan_r_a <= !fracta[22] & |fracta[21:0];
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always @(posedge clk)
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qnan_r_b <= fractb[22];
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always @(posedge clk)
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snan_r_b <= !fractb[22]; // & |fractb[21:0];
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always @(posedge clk)
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ind <= (expa_ff & infa_f_r); // & (expb_ff & infb_f_r);
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always @(posedge clk)
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inf <= (expa_ff & infa_f_r); // | (expb_ff & infb_f_r);
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always @(posedge clk)
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qnan <= (expa_ff & qnan_r_a); // | (expb_ff & qnan_r_b);
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always @(posedge clk)
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snan <= (expa_ff & snan_r_a); // | (expb_ff & snan_r_b);
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always @(posedge clk)
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opa_nan <= &expa & (|fracta[22:0]);
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always @(posedge clk)
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opb_nan <= &expb & (|fractb[22:0]);
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always @(posedge clk)
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opa_inf <= (expa_ff & infa_f_r);
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always @(posedge clk)
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opb_inf <= (expb_ff & infb_f_r);
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always @(posedge clk)
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expa_00 <= !(|expa);
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always @(posedge clk)
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expb_00 <= !(|expb);
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always @(posedge clk)
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fracta_00 <= !(|fracta);
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always @(posedge clk)
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fractb_00 <= !(|fractb);
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always @(posedge clk)
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opa_00 <= expa_00 & fracta_00;
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always @(posedge clk)
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opb_00 <= expb_00 & fractb_00;
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always @(posedge clk)
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opa_dn <= expa_00;
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always @(posedge clk)
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opb_dn <= expb_00;
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endmodule // or1200_fpu_intfloat_conv_except
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No newline at end of file
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No newline at end of file
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