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//////////////////////////////////////////////////////////////////////
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//// ////
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//// or1200_fpu_pre_norm_mul ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// Description ////
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//// pre-normalization entity for the multiplication unit ////
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//// ////
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//// To Do: ////
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//// ////
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//// ////
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//// Author(s): ////
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//// - Original design (FPU100) - ////
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//// Jidan Al-eryani, jidan@gmx.net ////
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//// - Conv. to Verilog and inclusion in OR1200 - ////
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//// Julius Baxter, julius@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2006, 2010
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//
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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//
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// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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module or1200_fpu_pre_norm_mul (
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clk_i,
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opa_i,
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opb_i,
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exp_10_o,
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fracta_24_o,
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fractb_24_o
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);
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parameter FP_WIDTH = 32;
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parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
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parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
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parameter FRAC_WIDTH = 23;
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parameter EXP_WIDTH = 8;
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parameter ZERO_VECTOR = 31'd0;
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parameter INF = 31'b1111111100000000000000000000000;
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parameter QNAN = 31'b1111111110000000000000000000000;
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parameter SNAN = 31'b1111111100000000000000000000001;
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input clk_i;
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input [FP_WIDTH-1:0] opa_i;
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input [FP_WIDTH-1:0] opb_i;
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output reg [EXP_WIDTH+1:0] exp_10_o;
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output [FRAC_WIDTH:0] fracta_24_o;
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output [FRAC_WIDTH:0] fractb_24_o;
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wire [EXP_WIDTH-1:0] s_expa;
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wire [EXP_WIDTH-1:0] s_expb;
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wire [FRAC_WIDTH-1:0] s_fracta;
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wire [FRAC_WIDTH-1:0] s_fractb;
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wire [EXP_WIDTH+1:0] s_exp_10_o;
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wire [EXP_WIDTH+1:0] s_expa_in;
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wire [EXP_WIDTH+1:0] s_expb_in;
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wire s_opa_dn, s_opb_dn;
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assign s_expa = opa_i[30:23];
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assign s_expb = opb_i[30:23];
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assign s_fracta = opa_i[22:0];
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assign s_fractb = opb_i[22:0];
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// Output Register
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always @(posedge clk_i)
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exp_10_o <= s_exp_10_o;
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// opa or opb is denormalized
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assign s_opa_dn = !(|s_expa);
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assign s_opb_dn = !(|s_expb);
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assign fracta_24_o = {!s_opa_dn, s_fracta};
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assign fractb_24_o = {!s_opb_dn, s_fractb};
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assign s_expa_in = {2'd0, s_expa} + {9'd0, s_opa_dn};
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assign s_expb_in = {2'd0, s_expb} + {9'd0, s_opb_dn};
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assign s_exp_10_o = s_expa_in + s_expb_in - 10'b0001111111;
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endmodule // or1200_fpu_pre_norm_mul
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