URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 363 |
Rev 499 |
Line 128... |
Line 128... |
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assign genpc_freeze = (du_stall & !saving_if_insn) | flushpipe_r;
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assign genpc_freeze = (du_stall & !saving_if_insn) | flushpipe_r;
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assign if_freeze = id_freeze | extend_flush;
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assign if_freeze = id_freeze | extend_flush;
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assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze
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assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze
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| (|waiting_on) | force_dslot_fetch) | du_stall | mac_stall;
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| (|waiting_on) | force_dslot_fetch) | du_stall;
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assign ex_freeze = wb_freeze;
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assign ex_freeze = wb_freeze;
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assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze
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assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze
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| (|waiting_on)) | du_stall | mac_stall | abort_ex;
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| (|waiting_on)) | du_stall | abort_ex;
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//
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//
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// registered flushpipe
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// registered flushpipe
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//
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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Line 169... |
Line 169... |
// Waiting on generation
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// Waiting on generation
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//
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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if (rst == `OR1200_RST_VALUE)
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waiting_on <= 0;
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waiting_on <= 0;
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else if ((waiting_on == `OR1200_WAIT_ON_MULTMAC) & !mac_stall)
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waiting_on <= 0;
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else if ((waiting_on == `OR1200_WAIT_ON_FPU) & fpu_done)
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else if ((waiting_on == `OR1200_WAIT_ON_FPU) & fpu_done)
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waiting_on <= 0;
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waiting_on <= 0;
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else if ((waiting_on == `OR1200_WAIT_ON_MTSPR) & mtspr_done)
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else if ((waiting_on == `OR1200_WAIT_ON_MTSPR) & mtspr_done)
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waiting_on <= 0;
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waiting_on <= 0;
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else if (!ex_freeze)
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else if (!ex_freeze)
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