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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's generate PC ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// Description ////
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//// PC, interface to IC. ////
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//// ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Log: or1200_genpc.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Structure reordered and bugs fixed.
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_genpc(
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// Clock and reset
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clk, rst,
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// External i/f to IC
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icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
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icpu_rty_i, icpu_adr_i,
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// Internal i/f
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pre_branch_op, branch_op, except_type, except_prefix,
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id_branch_addrtarget, ex_branch_addrtarget, muxed_b, operand_b,
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flag, flagforw, ex_branch_taken, except_start,
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epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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genpc_freeze, no_more_dslot
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);
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//
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// I/O
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//
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//
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// Clock and reset
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//
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input clk;
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input rst;
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//
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// External i/f to IC
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//
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output [31:0] icpu_adr_o;
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output icpu_cycstb_o;
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output [3:0] icpu_sel_o;
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output [3:0] icpu_tag_o;
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input icpu_rty_i;
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input [31:0] icpu_adr_i;
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//
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// Internal i/f
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//
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input [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op;
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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input except_prefix;
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input [31:2] id_branch_addrtarget;
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input [31:2] ex_branch_addrtarget;
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input [31:0] muxed_b;
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input [31:0] operand_b;
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input flag;
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input flagforw;
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output ex_branch_taken;
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input except_start;
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input [31:0] epcr;
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input [31:0] spr_dat_i;
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input spr_pc_we;
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input genpc_refetch;
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input genpc_freeze;
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input no_more_dslot;
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//
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// Internal wires and regs
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//
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reg [31:2] pcreg_default;
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wire [31:0] pcreg_boot;
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reg pcreg_select;
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reg [31:2] pcreg;
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reg [31:0] pc;
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// Set in event of jump or taken branch
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reg ex_branch_taken;
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reg genpc_refetch_r;
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//
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// Address of insn to be fecthed
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//
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assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we
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& (icpu_rty_i | genpc_refetch) ?
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icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};
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//
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// Control access to IC subsystem
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//
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assign icpu_cycstb_o = ~(genpc_freeze | (|pre_branch_op && !icpu_rty_i));
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assign icpu_sel_o = 4'b1111;
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assign icpu_tag_o = `OR1200_ITAG_NI;
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//
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// genpc_freeze_r
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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genpc_refetch_r <= 1'b0;
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else if (genpc_refetch)
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genpc_refetch_r <= 1'b1;
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else
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genpc_refetch_r <= 1'b0;
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//
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// Async calculation of new PC value. This value is used for addressing the
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// IC.
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//
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always @(pcreg or ex_branch_addrtarget or flag or branch_op or except_type
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or except_start or operand_b or epcr or spr_pc_we or spr_dat_i or
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except_prefix)
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begin
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casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
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{2'b00, `OR1200_BRANCHOP_NOP}: begin
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pc = {pcreg + 30'd1, 2'b0};
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ex_branch_taken = 1'b0;
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end
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{2'b00, `OR1200_BRANCHOP_J}: begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: BRANCHOP_J: pc <= ex_branch_addrtarget %h"
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, $time, ex_branch_addrtarget);
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// synopsys translate_on
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`endif
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pc = {ex_branch_addrtarget, 2'b00};
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ex_branch_taken = 1'b1;
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end
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{2'b00, `OR1200_BRANCHOP_JR}: begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: BRANCHOP_JR: pc <= operand_b %h",
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$time, operand_b);
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// synopsys translate_on
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`endif
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pc = operand_b;
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ex_branch_taken = 1'b1;
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end
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{2'b00, `OR1200_BRANCHOP_BF}:
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if (flag) begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: BRANCHOP_BF: pc <= ex_branch_addrtarget %h",
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$time, ex_branch_addrtarget);
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// synopsys translate_on
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`endif
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pc = {ex_branch_addrtarget, 2'b00};
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ex_branch_taken = 1'b1;
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end
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else begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: BRANCHOP_BF: not taken", $time);
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// synopsys translate_on
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`endif
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pc = {pcreg + 30'd1, 2'b0};
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ex_branch_taken = 1'b0;
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end
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{2'b00, `OR1200_BRANCHOP_BNF}:
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if (flag) begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: BRANCHOP_BNF: not taken", $time);
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// synopsys translate_on
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`endif
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pc = {pcreg + 30'd1, 2'b0};
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ex_branch_taken = 1'b0;
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end
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else begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: BRANCHOP_BNF: pc <= ex_branch_addrtarget %h",
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$time, ex_branch_addrtarget);
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// synopsys translate_on
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`endif
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pc = {ex_branch_addrtarget, 2'b00};
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ex_branch_taken = 1'b1;
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end
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{2'b00, `OR1200_BRANCHOP_RFE}: begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: BRANCHOP_RFE: pc <= epcr %h",
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$time, epcr);
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// synopsys translate_on
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`endif
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pc = epcr;
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ex_branch_taken = 1'b1;
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end
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{2'b01, 3'bxxx}: begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("Starting exception: %h.", except_type);
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// synopsys translate_on
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`endif
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pc = {(except_prefix ?
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`OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P),
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except_type, `OR1200_EXCEPT_V};
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ex_branch_taken = 1'b1;
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end
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default: begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("l.mtspr writing into PC: %h.", spr_dat_i);
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// synopsys translate_on
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`endif
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pc = spr_dat_i;
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ex_branch_taken = 1'b0;
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end
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endcase
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end
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//
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// PC register
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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// default value
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if (rst == `OR1200_RST_VALUE) begin
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pcreg_default <= `OR1200_BOOT_PCREG_DEFAULT; // jb
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pcreg_select <= 1'b1;// select async. value due to reset state
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end
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// selected value (different from default) is written into FF after
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// reset state
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else if (pcreg_select) begin
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// dynamic value can only be assigned to FF out of reset!
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pcreg_default <= pcreg_boot[31:2];
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pcreg_select <= 1'b0; // select FF value
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end
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else if (spr_pc_we) begin
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pcreg_default <= spr_dat_i[31:2];
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end
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else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i
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& !genpc_refetch) begin
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pcreg_default <= pc[31:2];
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end
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// select async. value for pcreg after reset - PC jumps to the address selected
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// after boot.
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assign pcreg_boot = `OR1200_BOOT_ADR; // changed JB
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always @(pcreg_boot or pcreg_default or pcreg_select)
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if (pcreg_select)
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// async. value is selected due to reset state
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pcreg = pcreg_boot[31:2];
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else
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// FF value is selected 2nd clock after reset state
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pcreg = pcreg_default ;
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endmodule
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