| Line 62... |
Line 62... |
// Internal i/f
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// Internal i/f
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pre_branch_op, branch_op, except_type, except_prefix,
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pre_branch_op, branch_op, except_type, except_prefix,
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id_branch_addrtarget, ex_branch_addrtarget, muxed_b, operand_b,
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id_branch_addrtarget, ex_branch_addrtarget, muxed_b, operand_b,
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flag, flagforw, ex_branch_taken, except_start,
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flag, flagforw, ex_branch_taken, except_start,
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epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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genpc_freeze, no_more_dslot
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genpc_freeze, no_more_dslot, lsu_stall
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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| Line 106... |
Line 106... |
input [31:0] spr_dat_i;
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input [31:0] spr_dat_i;
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input spr_pc_we;
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input spr_pc_we;
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input genpc_refetch;
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input genpc_refetch;
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input genpc_freeze;
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input genpc_freeze;
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input no_more_dslot;
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input no_more_dslot;
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input lsu_stall;
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parameter boot_adr = `OR1200_BOOT_ADR;
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parameter boot_adr = `OR1200_BOOT_ADR;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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| Line 118... |
Line 119... |
reg [31:2] pcreg;
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reg [31:2] pcreg;
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reg [31:0] pc;
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reg [31:0] pc;
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// Set in event of jump or taken branch
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// Set in event of jump or taken branch
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reg ex_branch_taken;
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reg ex_branch_taken;
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reg genpc_refetch_r;
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reg genpc_refetch_r;
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reg wait_lsu;
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//
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//
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// Address of insn to be fecthed
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// Address of insn to be fecthed
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//
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//
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assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we
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assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we
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| Line 129... |
Line 131... |
icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};
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icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};
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//
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//
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// Control access to IC subsystem
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// Control access to IC subsystem
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//
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//
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assign icpu_cycstb_o = ~(genpc_freeze | (|pre_branch_op && !icpu_rty_i));
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assign icpu_cycstb_o = ~(genpc_freeze | (|pre_branch_op && !icpu_rty_i) | wait_lsu);
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assign icpu_sel_o = 4'b1111;
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assign icpu_sel_o = 4'b1111;
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assign icpu_tag_o = `OR1200_ITAG_NI;
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assign icpu_tag_o = `OR1200_ITAG_NI;
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//
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//
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// wait_lsu
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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wait_lsu <= 1'b0;
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else if (!wait_lsu & |pre_branch_op & lsu_stall)
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wait_lsu <= 1'b1;
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else if (wait_lsu & ~|pre_branch_op)
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wait_lsu <= 1'b0;
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//
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// genpc_freeze_r
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// genpc_freeze_r
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//
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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if (rst == `OR1200_RST_VALUE)
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genpc_refetch_r <= 1'b0;
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genpc_refetch_r <= 1'b0;
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