| Line 100... |
Line 100... |
reg [1:0] state;
|
reg [1:0] state;
|
reg [2:0] cnt;
|
reg [2:0] cnt;
|
reg hitmiss_eval;
|
reg hitmiss_eval;
|
reg load;
|
reg load;
|
reg cache_inhibit;
|
reg cache_inhibit;
|
|
reg waiting_for_first_fill_ack; // JPB
|
|
|
//
|
//
|
// Generate of ICRAM write enables
|
// Generate of ICRAM write enables
|
//
|
//
|
assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
|
assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
|
| Line 142... |
Line 143... |
saved_addr_r <= 32'b0;
|
saved_addr_r <= 32'b0;
|
hitmiss_eval <= 1'b0;
|
hitmiss_eval <= 1'b0;
|
load <= 1'b0;
|
load <= 1'b0;
|
cnt <= 3'b000;
|
cnt <= 3'b000;
|
cache_inhibit <= 1'b0;
|
cache_inhibit <= 1'b0;
|
|
waiting_for_first_fill_ack <= 0; // JPB
|
|
|
end
|
end
|
else
|
else
|
case (state) // synopsys parallel_case
|
case (state) // synopsys parallel_case
|
`OR1200_ICFSM_IDLE :
|
`OR1200_ICFSM_IDLE :
|
if (ic_en & icqmem_cycstb_i) begin // fetch
|
if (ic_en & icqmem_cycstb_i) begin // fetch
|
state <= `OR1200_ICFSM_CFETCH;
|
state <= `OR1200_ICFSM_CFETCH;
|
saved_addr_r <= start_addr;
|
saved_addr_r <= start_addr;
|
hitmiss_eval <= 1'b1;
|
hitmiss_eval <= 1'b1;
|
load <= 1'b1;
|
load <= 1'b1;
|
cache_inhibit <= icqmem_ci_i;
|
cache_inhibit <= icqmem_ci_i;
|
|
waiting_for_first_fill_ack <= 0; // JPB
|
end
|
end
|
else begin // idle
|
else begin // idle
|
hitmiss_eval <= 1'b0;
|
hitmiss_eval <= 1'b0;
|
load <= 1'b0;
|
load <= 1'b0;
|
cache_inhibit <= 1'b0;
|
cache_inhibit <= 1'b0;
|
| Line 176... |
Line 180... |
(cache_inhibit & biudata_valid)) begin
|
(cache_inhibit & biudata_valid)) begin
|
state <= `OR1200_ICFSM_IDLE;
|
state <= `OR1200_ICFSM_IDLE;
|
hitmiss_eval <= 1'b0;
|
hitmiss_eval <= 1'b0;
|
load <= 1'b0;
|
load <= 1'b0;
|
cache_inhibit <= 1'b0;
|
cache_inhibit <= 1'b0;
|
|
waiting_for_first_fill_ack <= 0;
|
end // if ((!ic_en) ||...
|
end // if ((!ic_en) ||...
|
// fetch missed, finish current external fetch and refill
|
// fetch missed, finish current external fetch and refill
|
else if (tagcomp_miss & biudata_valid) begin
|
else if (tagcomp_miss & biudata_valid) begin
|
state <= `OR1200_ICFSM_LREFILL3;
|
state <= `OR1200_ICFSM_LREFILL3;
|
saved_addr_r[3:2] <= saved_addr_r[3:2] + 1'd1;
|
saved_addr_r[3:2] <= saved_addr_r[3:2] + 1'd1;
|
hitmiss_eval <= 1'b0;
|
hitmiss_eval <= 1'b0;
|
cnt <= `OR1200_ICLS-2;
|
cnt <= `OR1200_ICLS-2;
|
cache_inhibit <= 1'b0;
|
cache_inhibit <= 1'b0;
|
|
waiting_for_first_fill_ack <= 0; // JPB
|
end
|
end
|
// fetch aborted (usually caused by exception)
|
// fetch aborted (usually caused by exception)
|
else if (!icqmem_cycstb_i) begin
|
else if (!icqmem_cycstb_i) begin
|
state <= `OR1200_ICFSM_IDLE;
|
state <= `OR1200_ICFSM_IDLE;
|
hitmiss_eval <= 1'b0;
|
hitmiss_eval <= 1'b0;
|
load <= 1'b0;
|
load <= 1'b0;
|
cache_inhibit <= 1'b0;
|
cache_inhibit <= 1'b0;
|
|
waiting_for_first_fill_ack <= 0; // JPB
|
end
|
end
|
// fetch hit, finish immediately
|
// fetch hit, finish immediately
|
else if (!tagcomp_miss & !icqmem_ci_i) begin
|
else if (!tagcomp_miss & !icqmem_ci_i &
|
|
!waiting_for_first_fill_ack) begin
|
|
state <= `OR1200_ICFSM_IDLE; // JPB
|
|
load <= 1'b0; // JPB
|
|
hitmiss_eval <= 1'b0; // JPB
|
saved_addr_r <= start_addr;
|
saved_addr_r <= start_addr;
|
cache_inhibit <= 1'b0;
|
cache_inhibit <= 1'b0;
|
end
|
end
|
else // fetch in-progress
|
else // fetch in-progress
|
hitmiss_eval <= 1'b0;
|
hitmiss_eval <= 1'b0;
|
|
|
|
if (hitmiss_eval & tagcomp_miss) // JPB
|
|
waiting_for_first_fill_ack <= 1;
|
|
|
end
|
end
|
`OR1200_ICFSM_LREFILL3 : begin
|
`OR1200_ICFSM_LREFILL3 : begin
|
// abort because IC has just been turned off
|
// abort because IC has just been turned off
|
if (!ic_en) begin
|
if (!ic_en) begin
|
// invalidate before IC can be turned on
|
// invalidate before IC can be turned on
|
