| Line 100... |
Line 100... |
//
|
//
|
// Internal wires and regs
|
// Internal wires and regs
|
//
|
//
|
reg [31:0] saved_addr_r;
|
reg [31:0] saved_addr_r;
|
reg [1:0] state;
|
reg [1:0] state;
|
reg [2:0] cnt;
|
reg [`OR1200_ICLS-1:0] cnt;
|
reg hitmiss_eval;
|
reg hitmiss_eval;
|
reg load;
|
reg load;
|
reg cache_inhibit;
|
reg cache_inhibit;
|
reg last_eval_miss; // JPB
|
reg last_eval_miss; // JPB
|
|
|
| Line 145... |
Line 145... |
if (rst == `OR1200_RST_VALUE) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
state <= `OR1200_ICFSM_IDLE;
|
state <= `OR1200_ICFSM_IDLE;
|
saved_addr_r <= 32'b0;
|
saved_addr_r <= 32'b0;
|
hitmiss_eval <= 1'b0;
|
hitmiss_eval <= 1'b0;
|
load <= 1'b0;
|
load <= 1'b0;
|
cnt <= 3'b000;
|
cnt <= `OR1200_ICLS'd0;
|
cache_inhibit <= 1'b0;
|
cache_inhibit <= 1'b0;
|
last_eval_miss <= 0; // JPB
|
last_eval_miss <= 0; // JPB
|
|
|
end
|
end
|
else
|
else
|
| Line 172... |
Line 172... |
|
|
if (icqmem_cycstb_i & icqmem_ci_i)
|
if (icqmem_cycstb_i & icqmem_ci_i)
|
cache_inhibit <= 1'b1;
|
cache_inhibit <= 1'b1;
|
|
|
if (hitmiss_eval)
|
if (hitmiss_eval)
|
saved_addr_r[31:13] <= start_addr[31:13];
|
saved_addr_r[31:`OR1200_ICTAGL] <= start_addr[31:`OR1200_ICTAGL];
|
|
|
if ((!ic_en) ||
|
if ((!ic_en) ||
|
// fetch aborted (usually caused by IMMU)
|
// fetch aborted (usually caused by IMMU)
|
(hitmiss_eval & !icqmem_cycstb_i) ||
|
(hitmiss_eval & !icqmem_cycstb_i) ||
|
(biudata_error) || // fetch terminated with an error
|
(biudata_error) || // fetch terminated with an error
|
// fetch from cache-inhibited page
|
// fetch from cache-inhibited page
|
| Line 188... |
Line 187... |
cache_inhibit <= 1'b0;
|
cache_inhibit <= 1'b0;
|
end // if ((!ic_en) ||...
|
end // if ((!ic_en) ||...
|
// fetch missed, wait for first fetch and continue filling line
|
// fetch missed, wait for first fetch and continue filling line
|
else if (tagcomp_miss & biudata_valid) begin
|
else if (tagcomp_miss & biudata_valid) begin
|
state <= `OR1200_ICFSM_LREFILL3;
|
state <= `OR1200_ICFSM_LREFILL3;
|
saved_addr_r[3:2] <= saved_addr_r[3:2] + 1'd1;
|
saved_addr_r[`OR1200_ICLS-1:2]
|
|
<= saved_addr_r[`OR1200_ICLS-1:2] + 1;
|
hitmiss_eval <= 1'b0;
|
hitmiss_eval <= 1'b0;
|
cnt <= `OR1200_ICLS-2;
|
cnt <= ((1 << `OR1200_ICLS) - (2 * 4));
|
cache_inhibit <= 1'b0;
|
cache_inhibit <= 1'b0;
|
end
|
end
|
// fetch aborted (usually caused by exception)
|
// fetch aborted (usually caused by exception)
|
else if (!icqmem_cycstb_i
|
else if (!icqmem_cycstb_i
|
& !last_eval_miss // JPB
|
& !last_eval_miss // JPB
|
| Line 225... |
Line 225... |
hitmiss_eval <= 1'b0;
|
hitmiss_eval <= 1'b0;
|
load <= 1'b0;
|
load <= 1'b0;
|
end
|
end
|
// refill ack, more fetchs to come
|
// refill ack, more fetchs to come
|
else if (biudata_valid && (|cnt)) begin
|
else if (biudata_valid && (|cnt)) begin
|
cnt <= cnt - 3'd1;
|
cnt <= cnt - `OR1200_ICLS'd4;
|
saved_addr_r[3:2] <= saved_addr_r[3:2] + 1'd1;
|
saved_addr_r[`OR1200_ICLS-1:2]
|
|
<= saved_addr_r[`OR1200_ICLS-1:2] + 1;
|
end
|
end
|
// last fetch of line refill
|
// last fetch of line refill
|
else if (biudata_valid) begin
|
else if (biudata_valid) begin
|
state <= `OR1200_ICFSM_IDLE;
|
state <= `OR1200_ICFSM_IDLE;
|
saved_addr_r <= start_addr;
|
saved_addr_r <= start_addr;
|
