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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_ic_fsm.v] - Diff between revs 477 and 849

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Rev 477 Rev 849
Line 120... Line 120...
   assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
   assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
 
 
   //assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;
   //assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;
   assign saved_addr = saved_addr_r;
   assign saved_addr = saved_addr_r;
 
 
   //
   // Asserted when a cache hit occurs and the first word is ready/valid
   // Assert for cache hit first word ready
 
   // Assert for cache miss first word stored/loaded OK
 
   // Assert for cache miss first word stored/loaded with an error
 
   //
 
   assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval &
   assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval &
                          !tagcomp_miss & !cache_inhibit;
                          !tagcomp_miss & !cache_inhibit;
   assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
 
 
   // Asserted when a cache miss occurs, but the first word of the new
 
   // cache line is ready (on the bus)
 
   // Cache hits overpower bus data
 
   assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid &
 
                           ~first_hit_ack;
 
 
 
   // Asserted when a cache occurs, but there was a bus error with handling
 
   // the old line or fetching the new line
   assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
   assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
 
 
   //
   //
   // Assert burst when doing reload of complete cache line
   // Assert burst when doing reload of complete cache line
   //
   //
Line 173... Line 177...
             if (icqmem_cycstb_i & icqmem_ci_i)
             if (icqmem_cycstb_i & icqmem_ci_i)
               cache_inhibit <=  1'b1;
               cache_inhibit <=  1'b1;
 
 
             if (hitmiss_eval)
             if (hitmiss_eval)
               saved_addr_r[31:`OR1200_ICTAGL] <= start_addr[31:`OR1200_ICTAGL];
               saved_addr_r[31:`OR1200_ICTAGL] <= start_addr[31:`OR1200_ICTAGL];
 
 
 
             // Check for stopped cache loads
 
                 // instruction cache turned-off
             if ((!ic_en) ||
             if ((!ic_en) ||
                 // fetch aborted (usually caused by IMMU)
                 // fetch aborted (usually caused by IMMU)
                 (hitmiss_eval & !icqmem_cycstb_i) ||
                 (hitmiss_eval & !icqmem_cycstb_i) ||
                 (biudata_error) ||  // fetch terminated with an error
                 (biudata_error) ||  // fetch terminated with an error
                 // fetch from cache-inhibited page
                 // fetch from cache-inhibited page

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