| Line 120... |
Line 120... |
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
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assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
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//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;
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//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;
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assign saved_addr = saved_addr_r;
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assign saved_addr = saved_addr_r;
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//
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// Asserted when a cache hit occurs and the first word is ready/valid
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// Assert for cache hit first word ready
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded with an error
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//
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assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval &
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assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval &
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!tagcomp_miss & !cache_inhibit;
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!tagcomp_miss & !cache_inhibit;
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assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
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// Asserted when a cache miss occurs, but the first word of the new
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// cache line is ready (on the bus)
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// Cache hits overpower bus data
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assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid &
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~first_hit_ack;
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// Asserted when a cache occurs, but there was a bus error with handling
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// the old line or fetching the new line
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assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
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assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
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//
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//
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// Assert burst when doing reload of complete cache line
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// Assert burst when doing reload of complete cache line
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//
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//
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| Line 173... |
Line 177... |
if (icqmem_cycstb_i & icqmem_ci_i)
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if (icqmem_cycstb_i & icqmem_ci_i)
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cache_inhibit <= 1'b1;
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cache_inhibit <= 1'b1;
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if (hitmiss_eval)
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if (hitmiss_eval)
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saved_addr_r[31:`OR1200_ICTAGL] <= start_addr[31:`OR1200_ICTAGL];
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saved_addr_r[31:`OR1200_ICTAGL] <= start_addr[31:`OR1200_ICTAGL];
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// Check for stopped cache loads
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// instruction cache turned-off
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if ((!ic_en) ||
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if ((!ic_en) ||
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// fetch aborted (usually caused by IMMU)
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// fetch aborted (usually caused by IMMU)
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(hitmiss_eval & !icqmem_cycstb_i) ||
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(hitmiss_eval & !icqmem_cycstb_i) ||
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(biudata_error) || // fetch terminated with an error
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(biudata_error) || // fetch terminated with an error
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// fetch from cache-inhibited page
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// fetch from cache-inhibited page
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