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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's IC FSM ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// Description ////
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//// Insn cache state machine ////
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//// ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Log: or1200_ic_fsm.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Bugs fixed.
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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`define OR1200_ICFSM_IDLE 2'd0
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`define OR1200_ICFSM_CFETCH 2'd1
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`define OR1200_ICFSM_LREFILL3 2'd2
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`define OR1200_ICFSM_IFETCH 2'd3
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//
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// Data cache FSM for cache line of 16 bytes (4x singleword)
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//
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module or1200_ic_fsm(
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// Clock and reset
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clk, rst,
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// Internal i/f to top level IC
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ic_en, icqmem_cycstb_i, icqmem_ci_i,
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tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
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icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
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burst, tag_we
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);
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//
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// I/O
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//
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input clk;
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input rst;
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input ic_en;
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input icqmem_cycstb_i;
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input icqmem_ci_i;
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input tagcomp_miss;
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input biudata_valid;
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input biudata_error;
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input [31:0] start_addr;
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output [31:0] saved_addr;
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output [3:0] icram_we;
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output biu_read;
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output first_hit_ack;
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output first_miss_ack;
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output first_miss_err;
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output burst;
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output tag_we;
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//
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// Internal wires and regs
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//
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reg [31:0] saved_addr_r;
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reg [1:0] state;
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reg [2:0] cnt;
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reg hitmiss_eval;
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reg load;
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reg cache_inhibit;
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//
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// Generate of ICRAM write enables
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//
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assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
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assign tag_we = biu_read & biudata_valid & !cache_inhibit;
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//
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// BIU read and write
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//
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assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
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//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;
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assign saved_addr = saved_addr_r;
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//
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// Assert for cache hit first word ready
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded with an error
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//
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assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval &
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!tagcomp_miss & !cache_inhibit;
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assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
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assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
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//
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// Assert burst when doing reload of complete cache line
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//
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assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss &
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!cache_inhibit | (state == `OR1200_ICFSM_LREFILL3);
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//
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// Main IC FSM
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//
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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if (rst == `OR1200_RST_VALUE) begin
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state <= `OR1200_ICFSM_IDLE;
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saved_addr_r <= 32'b0;
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hitmiss_eval <= 1'b0;
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load <= 1'b0;
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cnt <= 3'b000;
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cache_inhibit <= 1'b0;
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end
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else
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case (state) // synopsys parallel_case
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`OR1200_ICFSM_IDLE :
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if (ic_en & icqmem_cycstb_i) begin // fetch
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state <= `OR1200_ICFSM_CFETCH;
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saved_addr_r <= start_addr;
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hitmiss_eval <= 1'b1;
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load <= 1'b1;
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cache_inhibit <= icqmem_ci_i;
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end
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else begin // idle
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hitmiss_eval <= 1'b0;
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load <= 1'b0;
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cache_inhibit <= 1'b0;
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end
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`OR1200_ICFSM_CFETCH: begin // fetch
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if (icqmem_cycstb_i & icqmem_ci_i)
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cache_inhibit <= 1'b1;
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if (hitmiss_eval)
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saved_addr_r[31:13] <= start_addr[31:13];
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if ((!ic_en) ||
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// fetch aborted (usually caused by IMMU)
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(hitmiss_eval & !icqmem_cycstb_i) ||
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(biudata_error) || // fetch terminated with an error
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// fetch from cache-inhibited page
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(cache_inhibit & biudata_valid)) begin
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state <= `OR1200_ICFSM_IDLE;
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hitmiss_eval <= 1'b0;
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load <= 1'b0;
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cache_inhibit <= 1'b0;
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end // if ((!ic_en) ||...
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// fetch missed, finish current external fetch and refill
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else if (tagcomp_miss & biudata_valid) begin
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state <= `OR1200_ICFSM_LREFILL3;
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saved_addr_r[3:2] <= saved_addr_r[3:2] + 1'd1;
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hitmiss_eval <= 1'b0;
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cnt <= `OR1200_ICLS-2;
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cache_inhibit <= 1'b0;
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end
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// fetch aborted (usually caused by exception)
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else if (!icqmem_cycstb_i) begin
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state <= `OR1200_ICFSM_IDLE;
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hitmiss_eval <= 1'b0;
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load <= 1'b0;
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cache_inhibit <= 1'b0;
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end
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// fetch hit, finish immediately
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else if (!tagcomp_miss & !icqmem_ci_i) begin
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saved_addr_r <= start_addr;
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cache_inhibit <= 1'b0;
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end
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else // fetch in-progress
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hitmiss_eval <= 1'b0;
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end
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`OR1200_ICFSM_LREFILL3 : begin
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// abort because IC has just been turned off
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if (!ic_en) begin
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// invalidate before IC can be turned on
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state <= `OR1200_ICFSM_IDLE;
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saved_addr_r <= start_addr;
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hitmiss_eval <= 1'b0;
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load <= 1'b0;
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end
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// refill ack, more fetchs to come
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else if (biudata_valid && (|cnt)) begin
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cnt <= cnt - 3'd1;
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saved_addr_r[3:2] <= saved_addr_r[3:2] + 1'd1;
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end
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// last fetch of line refill
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else if (biudata_valid) begin
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state <= `OR1200_ICFSM_IDLE;
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saved_addr_r <= start_addr;
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hitmiss_eval <= 1'b0;
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load <= 1'b0;
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end
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end
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default:
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state <= `OR1200_ICFSM_IDLE;
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endcase
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end
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endmodule
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