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Line 56... |
`define OR1200_ICFSM_CFETCH 2'd1
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`define OR1200_ICFSM_CFETCH 2'd1
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`define OR1200_ICFSM_LREFILL3 2'd2
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`define OR1200_ICFSM_LREFILL3 2'd2
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`define OR1200_ICFSM_IFETCH 2'd3
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`define OR1200_ICFSM_IFETCH 2'd3
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//
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//
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// Data cache FSM for cache line of 16 bytes (4x singleword)
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// Instruction cache FSM
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//
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//
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module or1200_ic_fsm(
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module or1200_ic_fsm(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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// Internal i/f to top level IC
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// Internal i/f to top level IC
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ic_en, icqmem_cycstb_i, icqmem_ci_i,
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ic_en, icqmem_cycstb_i, icqmem_ci_i,
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tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
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tagcomp_miss,
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icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
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biudata_valid, biudata_error,
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burst, tag_we
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start_addr, saved_addr,
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icram_we, tag_we,
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biu_read,
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first_hit_ack, first_miss_ack, first_miss_err,
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burst
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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Line 104... |
reg [1:0] state;
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reg [1:0] state;
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reg [2:0] cnt;
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reg [2:0] cnt;
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reg hitmiss_eval;
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reg hitmiss_eval;
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reg load;
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reg load;
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reg cache_inhibit;
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reg cache_inhibit;
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reg waiting_for_first_fill_ack; // JPB
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reg last_eval_miss; // JPB
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//
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//
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// Generate of ICRAM write enables
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// Generate of ICRAM write enables
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//
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//
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assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
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assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
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saved_addr_r <= 32'b0;
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saved_addr_r <= 32'b0;
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hitmiss_eval <= 1'b0;
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hitmiss_eval <= 1'b0;
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load <= 1'b0;
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load <= 1'b0;
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cnt <= 3'b000;
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cnt <= 3'b000;
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cache_inhibit <= 1'b0;
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cache_inhibit <= 1'b0;
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waiting_for_first_fill_ack <= 0; // JPB
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last_eval_miss <= 0; // JPB
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end
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end
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else
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else
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case (state) // synopsys parallel_case
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case (state) // synopsys parallel_case
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`OR1200_ICFSM_IDLE :
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`OR1200_ICFSM_IDLE :
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Line 159... |
state <= `OR1200_ICFSM_CFETCH;
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state <= `OR1200_ICFSM_CFETCH;
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saved_addr_r <= start_addr;
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saved_addr_r <= start_addr;
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hitmiss_eval <= 1'b1;
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hitmiss_eval <= 1'b1;
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load <= 1'b1;
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load <= 1'b1;
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cache_inhibit <= icqmem_ci_i;
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cache_inhibit <= icqmem_ci_i;
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waiting_for_first_fill_ack <= 0; // JPB
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last_eval_miss <= 0; // JPB
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end
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end
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else begin // idle
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else begin // idle
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hitmiss_eval <= 1'b0;
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hitmiss_eval <= 1'b0;
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load <= 1'b0;
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load <= 1'b0;
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cache_inhibit <= 1'b0;
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cache_inhibit <= 1'b0;
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Line 184... |
(cache_inhibit & biudata_valid)) begin
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(cache_inhibit & biudata_valid)) begin
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state <= `OR1200_ICFSM_IDLE;
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state <= `OR1200_ICFSM_IDLE;
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hitmiss_eval <= 1'b0;
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hitmiss_eval <= 1'b0;
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load <= 1'b0;
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load <= 1'b0;
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cache_inhibit <= 1'b0;
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cache_inhibit <= 1'b0;
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waiting_for_first_fill_ack <= 0;
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end // if ((!ic_en) ||...
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end // if ((!ic_en) ||...
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// fetch missed, finish current external fetch and refill
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// fetch missed, wait for first fetch and continue filling line
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else if (tagcomp_miss & biudata_valid) begin
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else if (tagcomp_miss & biudata_valid) begin
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state <= `OR1200_ICFSM_LREFILL3;
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state <= `OR1200_ICFSM_LREFILL3;
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saved_addr_r[3:2] <= saved_addr_r[3:2] + 1'd1;
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saved_addr_r[3:2] <= saved_addr_r[3:2] + 1'd1;
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hitmiss_eval <= 1'b0;
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hitmiss_eval <= 1'b0;
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cnt <= `OR1200_ICLS-2;
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cnt <= `OR1200_ICLS-2;
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cache_inhibit <= 1'b0;
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cache_inhibit <= 1'b0;
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waiting_for_first_fill_ack <= 0; // JPB
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end
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end
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// fetch aborted (usually caused by exception)
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// fetch aborted (usually caused by exception)
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else if (!icqmem_cycstb_i) begin
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else if (!icqmem_cycstb_i
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& !last_eval_miss // JPB
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) begin
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state <= `OR1200_ICFSM_IDLE;
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state <= `OR1200_ICFSM_IDLE;
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hitmiss_eval <= 1'b0;
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hitmiss_eval <= 1'b0;
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load <= 1'b0;
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load <= 1'b0;
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cache_inhibit <= 1'b0;
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cache_inhibit <= 1'b0;
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waiting_for_first_fill_ack <= 0; // JPB
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end
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end
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// fetch hit, finish immediately
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// fetch hit, wait in this state for now
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else if (!tagcomp_miss & !icqmem_ci_i &
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else if (!tagcomp_miss & !icqmem_ci_i) begin
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!waiting_for_first_fill_ack) begin
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state <= `OR1200_ICFSM_IDLE; // JPB
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load <= 1'b0; // JPB
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hitmiss_eval <= 1'b0; // JPB
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saved_addr_r <= start_addr;
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saved_addr_r <= start_addr;
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cache_inhibit <= 1'b0;
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cache_inhibit <= 1'b0;
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end
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end
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else // fetch in-progress
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else // fetch in-progress
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hitmiss_eval <= 1'b0;
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hitmiss_eval <= 1'b0;
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if (hitmiss_eval & tagcomp_miss) // JPB
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if (hitmiss_eval & !tagcomp_miss) // JPB
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waiting_for_first_fill_ack <= 1;
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last_eval_miss <= 1; // JPB
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end
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end
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`OR1200_ICFSM_LREFILL3 : begin
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`OR1200_ICFSM_LREFILL3 : begin
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// abort because IC has just been turned off
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// abort because IC has just been turned off
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if (!ic_en) begin
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if (!ic_en) begin
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