OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_ic_ram.v] - Diff between revs 477 and 482

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 477 Rev 482
Line 123... Line 123... 
      .we(we[0]),
 
      .we(we[0]),
 
      //.oe(1'b1),
 
      //.oe(1'b1),
 
      .addr(addr),
 
      .addr(addr),
 
      .di(datain),
 
      .di(datain),
 
      .doq(dataout)
 
      .doq(dataout)
 
 
 
`ifdef OR1200_RAM_PARITY
 
 
 
      , .p_err()
 
 
 
`endif
 
      );
 
      );
 
`endif
 
`endif
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.