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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_ic_ram.v] - Diff between revs 482 and 483

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Rev 482	Rev 483
Line 61...	Line 61...
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`mbist_si_i, mbist_so_o, mbist_ctrl_i,`	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
`endif	`endif

	`ifdef OR1200_RAM_PARITY
	`// Parity error indicator`
	`p_err,`
	`endif

`// Internal i/f`	`// Internal i/f`
`addr, en, we, datain, dataout`	`addr, en, we, datain, dataout`
`);`	`);`

parameter dw = `OR1200_OPERAND_WIDTH;	parameter dw = `OR1200_OPERAND_WIDTH;
Line 88...	Line 93...
`input mbist_si_i;`	`input mbist_si_i;`
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;	input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
`output mbist_so_o;`	`output mbist_so_o;`
`endif	`endif

	`ifdef OR1200_RAM_PARITY
	`output p_err;`
	`endif

`ifdef OR1200_NO_IC	`ifdef OR1200_NO_IC

`//`	`//`
`// Insn cache not implemented`	`// Insn cache not implemented`
`//`	`//`
`assign dataout = {dw{1'b0}};`	`assign dataout = {dw{1'b0}};`
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`assign mbist_so_o = mbist_si_i;`	`assign mbist_so_o = mbist_si_i;`
`endif	`endif

	`ifdef OR1200_RAM_PARITY
	`assign p_err = 0;`
	`endif

`else	`else

`//`	`//`
`// Instantiation of IC RAM block`	`// Instantiation of IC RAM block`
`//`	`//`
Line 116...	Line 129...
`// RAM BIST`	`// RAM BIST`
`.mbist_si_i(mbist_si_i),`	`.mbist_si_i(mbist_si_i),`
`.mbist_so_o(mbist_so_o),`	`.mbist_so_o(mbist_so_o),`
`.mbist_ctrl_i(mbist_ctrl_i),`	`.mbist_ctrl_i(mbist_ctrl_i),`
`endif	`endif
	`ifdef OR1200_RAM_PARITY
	`.p_err(p_err),`
	`endif
	`.rst(rst),`
`.clk(clk),`	`.clk(clk),`
`.ce(en),`	`.ce(en),`
`.we(we[0]),`	`.we(we[0]),`
`//.oe(1'b1),`	`//.oe(1'b1),`
`.addr(addr),`	`.addr(addr),`
`.di(datain),`	`.di(datain),`
`.doq(dataout)`	`.doq(dataout)`
`ifdef OR1200_RAM_PARITY
`, .p_err()`
`endif
`);`	`);`
`endif	`endif

`endmodule`	`endmodule`

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_ic_ram.v] - Diff between revs 482 and 483