Line 61... |
Line 61... |
`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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// Parity error indicator
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p_err,
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`endif
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// Internal i/f
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// Internal i/f
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addr, en, we, datain, tag_v, tag
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addr, en, we, datain, tag_v, tag
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);
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);
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parameter dw = `OR1200_ICTAG_W;
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parameter dw = `OR1200_ICTAG_W;
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Line 92... |
input mbist_si_i;
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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output mbist_so_o;
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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parameter tag_ram_extra_width = 24 - `OR1200_ICTAG_W;
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output p_err;
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wire [24-2:0] tag_wire;
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`else
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wire [dw-2:0] tag_wire;
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`endif
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//
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//
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// Internal i/f
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// Internal i/f
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//
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//
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input [aw-1:0] addr;
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input [aw-1:0] addr;
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input en;
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input en;
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input we;
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input we;
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input [dw-1:0] datain;
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input [dw-1:0] datain;
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output tag_v;
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output tag_v;
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output [dw-2:0] tag;
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output [dw-2:0] tag;
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`ifdef OR1200_NO_IC
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`ifdef OR1200_NO_IC
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//
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//
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// Insn cache not implemented
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// Insn cache not implemented
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//
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//
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assign tag = {dw-1{1'b0}};
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assign tag = {dw-1{1'b0}};
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assign tag_v = 1'b0;
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assign tag_v = 1'b0;
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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assign mbist_so_o = mbist_si_i;
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assign mbist_so_o = mbist_si_i;
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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assign p_err = 0;
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`endif
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`else
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`else
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assign tag = tag_wire[dw-2:0];
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//
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//
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// Instantiation of TAG RAM block
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// Instantiation of TAG RAM block
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//
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//
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or1200_spram #
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or1200_spram #
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(
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(
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.aw(`OR1200_ICTAG),
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.aw(`OR1200_ICTAG),
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`ifdef OR1200_RAM_PARITY
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.dw(24)
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`else
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.dw(`OR1200_ICTAG_W)
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.dw(`OR1200_ICTAG_W)
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`endif
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)
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)
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ic_tag0
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ic_tag0
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(
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(
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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.mbist_si_i(mbist_si_i),
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.mbist_si_i(mbist_si_i),
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.mbist_so_o(mbist_so_o),
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.mbist_so_o(mbist_so_o),
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.mbist_ctrl_i(mbist_ctrl_i),
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.mbist_ctrl_i(mbist_ctrl_i),
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`endif
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`endif
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.ce(en),
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.ce(en),
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.we(we),
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.we(we),
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//.oe(1'b1),
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//.oe(1'b1),
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.addr(addr),
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.addr(addr),
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.di(datain),
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.doq({tag, tag_v})
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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, .p_err()
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.p_err(p_err),
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.di({{tag_ram_extra_width{1'b0}},datain}),
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`else
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.di(datain),
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`endif
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`endif
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.doq({tag_wire, tag_v})
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);
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);
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`endif
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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