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//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////  OR1200's Data Cache top level                               ////
 
////                                                              ////
 
////  This file is part of the OpenRISC 1200 project              ////
 
////  http://opencores.org/project,or1k                           ////
 
////                                                              ////
 
////  Description                                                 ////
 
////  Instantiation of all IC blocks.                             ////
 
////                                                              ////
 
////  To Do:                                                      ////
 
////   - make it smaller and faster                               ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////      - Damjan Lampret, lampret@opencores.org                 ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
////                                                              ////
 
//// This source file is free software; you can redistribute it   ////
 
//// and/or modify it under the terms of the GNU Lesser General   ////
 
//// Public License as published by the Free Software Foundation; ////
 
//// either version 2.1 of the License, or (at your option) any   ////
 
//// later version.                                               ////
 
////                                                              ////
 
//// This source is distributed in the hope that it will be       ////
 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
 
//// details.                                                     ////
 
////                                                              ////
 
//// You should have received a copy of the GNU Lesser General    ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//
 
// $Log: or1200_ic_top.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// No update 
 
 
 
// synopsys translate_off
 
`include "timescale.v"
 
// synopsys translate_on
 
`include "or1200_defines.v"
 
 
 
//
 
// Data cache
 
//
 
module or1200_ic_top(
 
        // Rst, clk and clock control
 
        clk, rst,
 
 
 
        // External i/f
 
        icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o, icbiu_sel_o, icbiu_cab_o,
 
        icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
 
 
 
        // Internal i/f
 
        ic_en,
 
        icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i,
 
        icqmem_sel_i, icqmem_tag_i,
 
        icqmem_dat_o, icqmem_ack_o, icqmem_rty_o, icqmem_err_o, icqmem_tag_o,
 
 
 
`ifdef OR1200_BIST
 
        // RAM BIST
 
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
 
`endif
 
 
 
        // SPRs
 
        spr_cs, spr_write, spr_dat_i
 
);
 
 
 
parameter dw = `OR1200_OPERAND_WIDTH;
 
 
 
//
 
// I/O
 
//
 
 
 
//
 
// Clock and reset
 
//
 
input                           clk;
 
input                           rst;
 
 
 
//
 
// External I/F
 
//
 
output  [dw-1:0]         icbiu_dat_o;
 
output  [31:0]                   icbiu_adr_o;
 
output                          icbiu_cyc_o;
 
output                          icbiu_stb_o;
 
output                          icbiu_we_o;
 
output  [3:0]                    icbiu_sel_o;
 
output                          icbiu_cab_o;
 
input   [dw-1:0]         icbiu_dat_i;
 
input                           icbiu_ack_i;
 
input                           icbiu_err_i;
 
 
 
//
 
// Internal I/F
 
//
 
input                           ic_en;
 
input   [31:0]                   icqmem_adr_i;
 
input                           icqmem_cycstb_i;
 
input                           icqmem_ci_i;
 
input   [3:0]                    icqmem_sel_i;
 
input   [3:0]                    icqmem_tag_i;
 
output  [dw-1:0]         icqmem_dat_o;
 
output                          icqmem_ack_o;
 
output                          icqmem_rty_o;
 
output                          icqmem_err_o;
 
output  [3:0]                    icqmem_tag_o;
 
 
 
`ifdef OR1200_BIST
 
//
 
// RAM BIST
 
//
 
input mbist_si_i;
 
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
 
output mbist_so_o;
 
`endif
 
 
 
//
 
// SPR access
 
//
 
input                           spr_cs;
 
input                           spr_write;
 
input   [31:0]                   spr_dat_i;
 
 
 
//
 
// Internal wires and regs
 
//
 
wire                            tag_v;
 
wire    [`OR1200_ICTAG_W-2:0]    tag;
 
wire    [dw-1:0]         to_icram;
 
wire    [dw-1:0]         from_icram;
 
wire    [31:0]                   saved_addr;
 
wire    [3:0]                    icram_we;
 
wire                            ictag_we;
 
wire    [31:0]                   ic_addr;
 
wire                            icfsm_biu_read;
 
reg                             tagcomp_miss;
 
wire    [`OR1200_ICINDXH:`OR1200_ICLS]  ictag_addr;
 
wire                            ictag_en;
 
wire                            ictag_v;
 
wire                            ic_inv;
 
wire                            icfsm_first_hit_ack;
 
wire                            icfsm_first_miss_ack;
 
wire                            icfsm_first_miss_err;
 
wire                            icfsm_burst;
 
wire                            icfsm_tag_we;
 
`ifdef OR1200_BIST
 
//
 
// RAM BIST
 
//
 
wire                            mbist_ram_so;
 
wire                            mbist_tag_so;
 
wire                            mbist_ram_si = mbist_si_i;
 
wire                            mbist_tag_si = mbist_ram_so;
 
assign                          mbist_so_o = mbist_tag_so;
 
`endif
 
 
 
//
 
// Simple assignments
 
//
 
assign icbiu_adr_o = ic_addr;
 
assign ic_inv = spr_cs & spr_write;
 
assign ictag_we = icfsm_tag_we | ic_inv;
 
assign ictag_addr = ic_inv ?
 
                    spr_dat_i[`OR1200_ICINDXH:`OR1200_ICLS] :
 
                    ic_addr[`OR1200_ICINDXH:`OR1200_ICLS];
 
assign ictag_en = ic_inv | ic_en;
 
assign ictag_v = ~ic_inv;
 
 
 
//
 
// Data to BIU is from ICRAM when IC is enabled or from LSU when
 
// IC is disabled
 
//
 
assign icbiu_dat_o = 32'h00000000;
 
 
 
//
 
// Bypases of the IC when IC is disabled
 
//
 
assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
 
assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
 
assign icbiu_we_o = 1'b0;
 
assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icqmem_sel_i;
 
assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
 
assign icqmem_rty_o = ~icqmem_ack_o & ~icqmem_err_o;
 
assign icqmem_tag_o = icqmem_err_o ? `OR1200_ITAG_BE : icqmem_tag_i;
 
 
 
//
 
// CPU normal and error termination
 
//
 
assign icqmem_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) : icbiu_ack_i;
 
assign icqmem_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i;
 
 
 
//
 
// Select between claddr generated by IC FSM and addr[3:2] generated by LSU
 
//
 
assign ic_addr = (icfsm_biu_read) ? saved_addr : icqmem_adr_i;
 
 
 
//
 
// Select between input data generated by LSU or by BIU
 
//
 
assign to_icram = icbiu_dat_i;
 
 
 
//
 
// Select between data generated by ICRAM or passed by BIU
 
//
 
assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
 
 
 
//
 
// Tag comparison
 
//
 
always @(tag or saved_addr or tag_v) begin
 
        if ((tag != saved_addr[31:`OR1200_ICTAGL]) || !tag_v)
 
                tagcomp_miss = 1'b1;
 
        else
 
                tagcomp_miss = 1'b0;
 
end
 
 
 
//
 
// Instantiation of IC Finite State Machine
 
//
 
or1200_ic_fsm or1200_ic_fsm(
 
        .clk(clk),
 
        .rst(rst),
 
        .ic_en(ic_en),
 
        .icqmem_cycstb_i(icqmem_cycstb_i),
 
        .icqmem_ci_i(icqmem_ci_i),
 
        .tagcomp_miss(tagcomp_miss),
 
        .biudata_valid(icbiu_ack_i),
 
        .biudata_error(icbiu_err_i),
 
        .start_addr(icqmem_adr_i),
 
        .saved_addr(saved_addr),
 
        .icram_we(icram_we),
 
        .biu_read(icfsm_biu_read),
 
        .first_hit_ack(icfsm_first_hit_ack),
 
        .first_miss_ack(icfsm_first_miss_ack),
 
        .first_miss_err(icfsm_first_miss_err),
 
        .burst(icfsm_burst),
 
        .tag_we(icfsm_tag_we)
 
);
 
 
 
//
 
// Instantiation of IC main memory
 
//
 
or1200_ic_ram or1200_ic_ram(
 
        .clk(clk),
 
        .rst(rst),
 
`ifdef OR1200_BIST
 
        // RAM BIST
 
        .mbist_si_i(mbist_ram_si),
 
        .mbist_so_o(mbist_ram_so),
 
        .mbist_ctrl_i(mbist_ctrl_i),
 
`endif
 
        .addr(ic_addr[`OR1200_ICINDXH:2]),
 
        .en(ic_en),
 
        .we(icram_we),
 
        .datain(to_icram),
 
        .dataout(from_icram)
 
);
 
 
 
//
 
// Instantiation of IC TAG memory
 
//
 
or1200_ic_tag or1200_ic_tag(
 
        .clk(clk),
 
        .rst(rst),
 
`ifdef OR1200_BIST
 
        // RAM BIST
 
        .mbist_si_i(mbist_tag_si),
 
        .mbist_so_o(mbist_tag_so),
 
        .mbist_ctrl_i(mbist_ctrl_i),
 
`endif
 
        .addr(ictag_addr),
 
        .en(ictag_en),
 
        .we(ictag_we),
 
        .datain({ic_addr[31:`OR1200_ICTAGL], ictag_v}),
 
        .tag_v(tag_v),
 
        .tag(tag)
 
);
 
 
 
endmodule
 
 
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