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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_ic_top.v] - Diff between revs 360 and 415

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  OR1200's Data Cache top level                               ////
////  OR1200's Instruction Cache top level                        ////
////                                                              ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://opencores.org/project,or1k                           ////
////  http://opencores.org/project,or1k                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 49... Line 49...
`include "timescale.v"
`include "timescale.v"
// synopsys translate_on
// synopsys translate_on
`include "or1200_defines.v"
`include "or1200_defines.v"
 
 
//
//
// Data cache
// Instruction cache top
//
//
module or1200_ic_top(
module or1200_ic_top(
        // Rst, clk and clock control
        // Rst, clk and clock control
        clk, rst,
        clk, rst,
 
 
        // External i/f
        // External i/f
        icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o, icbiu_sel_o, icbiu_cab_o,
        icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o,
        icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
        icbiu_sel_o, icbiu_cab_o, icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
 
 
        // Internal i/f
        // Internal i/f
        ic_en,
        ic_en,
        icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i,
        icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i, icqmem_sel_i, icqmem_tag_i,
        icqmem_sel_i, icqmem_tag_i,
 
        icqmem_dat_o, icqmem_ack_o, icqmem_rty_o, icqmem_err_o, icqmem_tag_o,
        icqmem_dat_o, icqmem_ack_o, icqmem_rty_o, icqmem_err_o, icqmem_tag_o,
 
 
`ifdef OR1200_BIST
`ifdef OR1200_BIST
        // RAM BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
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wire    [31:0]                   saved_addr;
wire    [31:0]                   saved_addr;
wire    [3:0]                    icram_we;
wire    [3:0]                    icram_we;
wire                            ictag_we;
wire                            ictag_we;
wire    [31:0]                   ic_addr;
wire    [31:0]                   ic_addr;
wire                            icfsm_biu_read;
wire                            icfsm_biu_read;
 
/* verilator lint_off UNOPTFLAT */
reg                             tagcomp_miss;
reg                             tagcomp_miss;
 
/* verilator lint_on UNOPTFLAT */
wire    [`OR1200_ICINDXH:`OR1200_ICLS]  ictag_addr;
wire    [`OR1200_ICINDXH:`OR1200_ICLS]  ictag_addr;
wire                            ictag_en;
wire                            ictag_en;
wire                            ictag_v;
wire                            ictag_v;
wire                            ic_inv;
wire                            ic_inv;
wire                            icfsm_first_hit_ack;
wire                            icfsm_first_hit_ack;
wire                            icfsm_first_miss_ack;
wire                            icfsm_first_miss_ack;
wire                            icfsm_first_miss_err;
wire                            icfsm_first_miss_err;
wire                            icfsm_burst;
wire                            icfsm_burst;
wire                            icfsm_tag_we;
wire                            icfsm_tag_we;
 
reg                             ic_inv_q;
 
 
`ifdef OR1200_BIST
`ifdef OR1200_BIST
//
//
// RAM BIST
// RAM BIST
//
//
wire                            mbist_ram_so;
wire                            mbist_ram_so;
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// Select between data generated by ICRAM or passed by BIU
// Select between data generated by ICRAM or passed by BIU
//
//
assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
 
 
//
//
 
// Detect falling edge of IC invalidate signal
 
// 
 
always @(posedge clk or `OR1200_RST_EVENT rst)
 
   if (rst==`OR1200_RST_VALUE)
 
     ic_inv_q <= 1'b0;
 
   else
 
     ic_inv_q <= ic_inv;
 
 
 
 
 
//
// Tag comparison
// Tag comparison
//
//
 
// During line invalidate, ensure it stays the same
 
//   /* TODO - do this properly! */
always @(tag or saved_addr or tag_v) begin
always @(tag or saved_addr or tag_v) begin
        if ((tag != saved_addr[31:`OR1200_ICTAGL]) || !tag_v)
          if ((tag != saved_addr[31:`OR1200_ICTAGL]) | !tag_v)
                tagcomp_miss = 1'b1;
            tagcomp_miss = (ic_inv | ic_inv_q) ? tagcomp_miss : 1'b1;
        else
        else
                tagcomp_miss = 1'b0;
            tagcomp_miss = (ic_inv | ic_inv_q) ? tagcomp_miss : 1'b0;
end
end
 
 
//
//
// Instantiation of IC Finite State Machine
// Instantiation of IC Finite State Machine
//
//

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