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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Data Cache top level ////
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//// OR1200's Instruction Cache top level ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://opencores.org/project,or1k ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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//
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//
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// Data cache
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// Instruction cache top
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//
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//
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module or1200_ic_top(
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module or1200_ic_top(
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// Rst, clk and clock control
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// Rst, clk and clock control
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clk, rst,
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clk, rst,
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// External i/f
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// External i/f
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icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o, icbiu_sel_o, icbiu_cab_o,
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icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o,
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icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
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icbiu_sel_o, icbiu_cab_o, icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
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// Internal i/f
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// Internal i/f
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ic_en,
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ic_en,
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icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i,
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icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i, icqmem_sel_i, icqmem_tag_i,
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icqmem_sel_i, icqmem_tag_i,
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icqmem_dat_o, icqmem_ack_o, icqmem_rty_o, icqmem_err_o, icqmem_tag_o,
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icqmem_dat_o, icqmem_ack_o, icqmem_rty_o, icqmem_err_o, icqmem_tag_o,
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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wire [31:0] saved_addr;
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wire [31:0] saved_addr;
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wire [3:0] icram_we;
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wire [3:0] icram_we;
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wire ictag_we;
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wire ictag_we;
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wire [31:0] ic_addr;
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wire [31:0] ic_addr;
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wire icfsm_biu_read;
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wire icfsm_biu_read;
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/* verilator lint_off UNOPTFLAT */
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reg tagcomp_miss;
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reg tagcomp_miss;
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/* verilator lint_on UNOPTFLAT */
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wire [`OR1200_ICINDXH:`OR1200_ICLS] ictag_addr;
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wire [`OR1200_ICINDXH:`OR1200_ICLS] ictag_addr;
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wire ictag_en;
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wire ictag_en;
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wire ictag_v;
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wire ictag_v;
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wire ic_inv;
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wire ic_inv;
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wire icfsm_first_hit_ack;
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wire icfsm_first_hit_ack;
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wire icfsm_first_miss_ack;
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wire icfsm_first_miss_ack;
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wire icfsm_first_miss_err;
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wire icfsm_first_miss_err;
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wire icfsm_burst;
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wire icfsm_burst;
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wire icfsm_tag_we;
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wire icfsm_tag_we;
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reg ic_inv_q;
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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//
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//
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// RAM BIST
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// RAM BIST
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//
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//
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wire mbist_ram_so;
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wire mbist_ram_so;
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// Select between data generated by ICRAM or passed by BIU
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// Select between data generated by ICRAM or passed by BIU
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//
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//
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assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
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assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
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//
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//
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// Detect falling edge of IC invalidate signal
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst==`OR1200_RST_VALUE)
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ic_inv_q <= 1'b0;
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else
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ic_inv_q <= ic_inv;
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//
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// Tag comparison
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// Tag comparison
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//
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//
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// During line invalidate, ensure it stays the same
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// /* TODO - do this properly! */
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always @(tag or saved_addr or tag_v) begin
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always @(tag or saved_addr or tag_v) begin
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if ((tag != saved_addr[31:`OR1200_ICTAGL]) || !tag_v)
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if ((tag != saved_addr[31:`OR1200_ICTAGL]) | !tag_v)
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tagcomp_miss = 1'b1;
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tagcomp_miss = (ic_inv | ic_inv_q) ? tagcomp_miss : 1'b1;
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else
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else
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tagcomp_miss = 1'b0;
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tagcomp_miss = (ic_inv | ic_inv_q) ? tagcomp_miss : 1'b0;
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end
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end
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//
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//
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// Instantiation of IC Finite State Machine
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// Instantiation of IC Finite State Machine
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//
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//
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