URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_ic_top.v] - Diff between revs 415 and 426

Rev 415	Rev 426
Line 231...	Line 231...

`//`	`//`
`// Tag comparison`	`// Tag comparison`
`//`	`//`
`// During line invalidate, ensure it stays the same`	`// During line invalidate, ensure it stays the same`
`// /* TODO - do this properly! */`
`always @(tag or saved_addr or tag_v) begin`	`always @(tag or saved_addr or tag_v) begin`
if ((tag != saved_addr[31:`OR1200_ICTAGL]) \| !tag_v)	if ((tag != saved_addr[31:`OR1200_ICTAGL]) \| !tag_v)
`tagcomp_miss = (ic_inv \| ic_inv_q) ? tagcomp_miss : 1'b1;`	`tagcomp_miss = 1'b1;`
`else`	`else`
`tagcomp_miss = (ic_inv \| ic_inv_q) ? tagcomp_miss : 1'b0;`	`tagcomp_miss = 1'b0;`
`end`	`end`

`//`	`//`
`// Instantiation of IC Finite State Machine`	`// Instantiation of IC Finite State Machine`
`//`	`//`