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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_ic_top.v] - Diff between revs 426 and 483

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Rev 426 Rev 483
Line 69... Line 69... 
`ifdef OR1200_BIST
 
`ifdef OR1200_BIST
 
        // RAM BIST
 
        // RAM BIST
 
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
 
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
 
`endif
 
`endif
 
 
 
 
 
 
 
`ifdef OR1200_RAM_PARITY
 
 
 
        // Parity error indicator
 
 
 
        p_err,
 
 
 
`endif
 
 
 
 
 
        // SPRs
 
        // SPRs
 
        spr_cs, spr_write, spr_dat_i
 
        spr_cs, spr_write, spr_dat_i
 
);
 
);
 
 
 
 
 
parameter dw = `OR1200_OPERAND_WIDTH;
 
parameter dw = `OR1200_OPERAND_WIDTH;
Line 123... Line 128... 
input mbist_si_i;
 
input mbist_si_i;
 
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
 
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
 
output mbist_so_o;
 
output mbist_so_o;
 
`endif
 
`endif
 
 
 
 
 
 
 
`ifdef OR1200_RAM_PARITY
 
 
 
output [1:0]                     p_err;
 
 
 
`endif
 
 
 
 
 
//
 
//
 
// SPR access
 
// SPR access
 
//
 
//
 
input                           spr_cs;
 
input                           spr_cs;
 
input                           spr_write;
 
input                           spr_write;
Line 142... Line 151... 
wire    [31:0]                   saved_addr;
 
wire    [31:0]                   saved_addr;
 
wire    [3:0]                    icram_we;
 
wire    [3:0]                    icram_we;
 
wire                            ictag_we;
 
wire                            ictag_we;
 
wire    [31:0]                   ic_addr;
 
wire    [31:0]                   ic_addr;
 
wire                            icfsm_biu_read;
 
wire                            icfsm_biu_read;
 
/* verilator lint_off UNOPTFLAT */
 
 
 
reg                             tagcomp_miss;
 
//reg                           tagcomp_miss;
 
/* verilator lint_on UNOPTFLAT */
 
   wire                         tagcomp_miss;
 
 
 
 
 
wire    [`OR1200_ICINDXH:`OR1200_ICLS]  ictag_addr;
 
wire    [`OR1200_ICINDXH:`OR1200_ICLS]  ictag_addr;
 
wire                            ictag_en;
 
wire                            ictag_en;
 
wire                            ictag_v;
 
wire                            ictag_v;
 
wire                            ic_inv;
 
wire                            ic_inv;
 
wire                            icfsm_first_hit_ack;
 
wire                            icfsm_first_hit_ack;
Line 167... Line 177... 
wire                            mbist_ram_si = mbist_si_i;
 
wire                            mbist_ram_si = mbist_si_i;
 
wire                            mbist_tag_si = mbist_ram_so;
 
wire                            mbist_tag_si = mbist_ram_so;
 
assign                          mbist_so_o = mbist_tag_so;
 
assign                          mbist_so_o = mbist_tag_so;
 
`endif
 
`endif
 
 
 
 
 
 
 
`ifdef OR1200_RAM_PARITY
 
 
 
wire [1:0]                       p_err_wire;
 
 
 
// Indicate an error if we're reading from the RAM (hit)
 
 
 
// Additionally, mask with tag_v as tag ram is properly cleared during
 
 
 
// init, whereas the instruction RAM is not.
 
 
 
assign p_err[0] = (icqmem_ack_o & (!icfsm_first_miss_ack | ic_en)) &
 
 
 
                  (tag_v & !p_err[1]) ? p_err_wire[0] : 0;
 
 
 
// Whenever there's a tag parity error and we have an instruction fetch
 
 
 
assign p_err[1] = (ictag_en & !ictag_we) ? p_err_wire[1] : 0;
 
 
 
 
 
 
 
`else
 
 
 
 
 
 
 
`endif
 
 
 
 
 
//
 
//
 
// Simple assignments
 
// Simple assignments
 
//
 
//
 
assign icbiu_adr_o = ic_addr;
 
assign icbiu_adr_o = ic_addr;
 
assign ic_inv = spr_cs & spr_write;
 
assign ic_inv = spr_cs & spr_write;
Line 231... Line 255... 
 
 
 
 
//
 
//
 
// Tag comparison
 
// Tag comparison
 
//
 
//
 
// During line invalidate, ensure it stays the same
 
// During line invalidate, ensure it stays the same
 
always @(tag or saved_addr or tag_v) begin
 
assign tagcomp_miss = ((tag != saved_addr[31:`OR1200_ICTAGL]) | !tag_v
 
          if ((tag != saved_addr[31:`OR1200_ICTAGL]) | !tag_v)
 
`ifdef OR1200_RAM_PARITY
 
            tagcomp_miss = 1'b1;
 
              | (|p_err_wire)
 
          else
 
`endif
 
            tagcomp_miss = 1'b0;
 
                          );
 
end
 
 
 
 
 
 
 
//
 
//
 
// Instantiation of IC Finite State Machine
 
// Instantiation of IC Finite State Machine
 
//
 
//
 
or1200_ic_fsm or1200_ic_fsm(
 
or1200_ic_fsm or1200_ic_fsm(
Line 273... Line 296... 
        // RAM BIST
 
        // RAM BIST
 
        .mbist_si_i(mbist_ram_si),
 
        .mbist_si_i(mbist_ram_si),
 
        .mbist_so_o(mbist_ram_so),
 
        .mbist_so_o(mbist_ram_so),
 
        .mbist_ctrl_i(mbist_ctrl_i),
 
        .mbist_ctrl_i(mbist_ctrl_i),
 
`endif
 
`endif
 
 
 
`ifdef OR1200_RAM_PARITY
 
 
 
        .p_err(p_err_wire[0]),
 
 
 
`endif
 
        .addr(ic_addr[`OR1200_ICINDXH:2]),
 
        .addr(ic_addr[`OR1200_ICINDXH:2]),
 
        .en(ic_en),
 
        .en(ic_en),
 
        .we(icram_we),
 
        .we(icram_we),
 
        .datain(to_icram),
 
        .datain(to_icram),
 
        .dataout(from_icram)
 
        .dataout(from_icram)
Line 292... Line 318... 
        // RAM BIST
 
        // RAM BIST
 
        .mbist_si_i(mbist_tag_si),
 
        .mbist_si_i(mbist_tag_si),
 
        .mbist_so_o(mbist_tag_so),
 
        .mbist_so_o(mbist_tag_so),
 
        .mbist_ctrl_i(mbist_ctrl_i),
 
        .mbist_ctrl_i(mbist_ctrl_i),
 
`endif
 
`endif
 
 
 
`ifdef OR1200_RAM_PARITY
 
 
 
        .p_err(p_err_wire[1]),
 
 
 
`endif
 
        .addr(ictag_addr),
 
        .addr(ictag_addr),
 
        .en(ictag_en),
 
        .en(ictag_en),
 
        .we(ictag_we),
 
        .we(ictag_we),
 
        .datain({ic_addr[31:`OR1200_ICTAGL], ictag_v}),
 
        .datain({ic_addr[31:`OR1200_ICTAGL], ictag_v}),
 
        .tag_v(tag_v),
 
        .tag_v(tag_v),

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