Line 67... |
Line 67... |
`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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// Parity error indicator
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p_err,
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`endif
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// SPR access
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// SPR access
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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Line 104... |
Line 109... |
input mbist_si_i;
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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output mbist_so_o;
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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output [1:0] p_err;
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`endif
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//
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//
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// SPR access
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// SPR access
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//
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//
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input spr_cs;
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input spr_cs;
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input spr_write;
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input spr_write;
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Line 122... |
Line 131... |
wire v;
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wire v;
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wire [`OR1200_ITLB_INDXW-1:0] tlb_index;
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wire [`OR1200_ITLB_INDXW-1:0] tlb_index;
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wire tlb_mr_en;
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wire tlb_mr_en;
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wire tlb_mr_we;
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wire tlb_mr_we;
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wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_in;
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wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_in;
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wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_out;
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wire tlb_tr_en;
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wire tlb_tr_en;
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wire tlb_tr_we;
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wire tlb_tr_we;
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wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_in;
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wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_in;
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`ifdef OR1200_RAM_PARITY
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wire [`OR1200_ITLBMRW-1+2:0] tlb_mr_ram_out;
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wire [`OR1200_ITLBTRW-1+2:0] tlb_tr_ram_out;
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`else
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wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_out;
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wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_out;
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wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_out;
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`endif
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// BIST
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// BIST
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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wire itlb_mr_ram_si;
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wire itlb_mr_ram_si;
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wire itlb_mr_ram_so;
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wire itlb_mr_ram_so;
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wire itlb_tr_ram_si;
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wire itlb_tr_ram_si;
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wire itlb_tr_ram_so;
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wire itlb_tr_ram_so;
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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wire [1:0] p_err_wire;
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reg p_err_en;
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`endif
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//
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//
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// Implemented bits inside match and translate registers
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// Implemented bits inside match and translate registers
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//
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//
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// itlbwYmrX: vpn 31-19 v 0
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// itlbwYmrX: vpn 31-19 v 0
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// itlbwYtrX: ppn 31-13 uxe 7 sxe 6
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// itlbwYtrX: ppn 31-13 uxe 7 sxe 6
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Line 181... |
Line 201... |
32'h00000000;
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32'h00000000;
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//
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//
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// Assign outputs from Match registers
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// Assign outputs from Match registers
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//
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//
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assign {vpn, v} = tlb_mr_ram_out;
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assign {vpn, v} = tlb_mr_ram_out[`OR1200_ITLBMRW-1:0];
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//
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//
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// Assign to Match registers inputs
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// Assign to Match registers inputs
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//
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//
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assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]};
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assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG],
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spr_dat_i[`OR1200_ITLBMR_V_BITS]};
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//
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//
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// Assign outputs from Translate registers
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// Assign outputs from Translate registers
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//
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//
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assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out;
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assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out[`OR1200_ITLBTRW-1:0];
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//
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//
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// Assign to Translate registers inputs
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// Assign to Translate registers inputs
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//
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//
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assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
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assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
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Line 204... |
Line 225... |
spr_dat_i[`OR1200_ITLBTR_CI_BITS]};
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spr_dat_i[`OR1200_ITLBTR_CI_BITS]};
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//
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//
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// Generate hit
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// Generate hit
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//
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//
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assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v;
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assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v
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`ifdef OR1200_RAM_PARITY
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& !p_err
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`endif
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;
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//
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//
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// TLB index is normally vaddr[18:13]. If it is SPR access then index is
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// TLB index is normally vaddr[18:13]. If it is SPR access then index is
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// spr_addr[5:0].
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// spr_addr[5:0].
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//
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//
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assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];
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assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] :
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vaddr[`OR1200_ITLB_INDX];
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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assign itlb_mr_ram_si = mbist_si_i;
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assign itlb_mr_ram_si = mbist_si_i;
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assign itlb_tr_ram_si = itlb_mr_ram_so;
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assign itlb_tr_ram_si = itlb_mr_ram_so;
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assign mbist_so_o = itlb_tr_ram_so;
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assign mbist_so_o = itlb_tr_ram_so;
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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always @(posedge clk)
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if (rst)
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p_err_en <= 0;
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else
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p_err_en <= (tlb_mr_en & !tlb_mr_we) | (tlb_tr_en & !tlb_tr_we);
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assign p_err = (p_err_en & (tlb_mr_en & !tlb_mr_we) |
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(tlb_tr_en & !tlb_tr_we)) ? p_err_wire : 0;
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`endif
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//
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//
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// Instantiation of ITLB Match Registers
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// Instantiation of ITLB Match Registers
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//
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//
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or1200_spram #
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or1200_spram #
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(
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(
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.aw(6),
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.aw(6),
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`ifdef OR1200_RAM_PARITY
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.dw(16)
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`else
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.dw(14)
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.dw(14)
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`endif
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)
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)
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itlb_mr_ram
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itlb_mr_ram
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(
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(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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.mbist_si_i(itlb_mr_ram_si),
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.mbist_si_i(itlb_mr_ram_si),
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.mbist_so_o(itlb_mr_ram_so),
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.mbist_so_o(itlb_mr_ram_so),
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.mbist_ctrl_i(mbist_ctrl_i),
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.mbist_ctrl_i(mbist_ctrl_i),
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`endif
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`endif
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.ce(tlb_mr_en),
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.ce(tlb_mr_en),
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.we(tlb_mr_we),
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.we(tlb_mr_we),
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//.oe(1'b1),
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//.oe(1'b1),
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.addr(tlb_index),
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.addr(tlb_index),
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.di(tlb_mr_ram_in),
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.doq(tlb_mr_ram_out)
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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, .p_err()
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.p_err(p_err_wire[0]),
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.di({2'b00,tlb_mr_ram_in}),
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`else
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.di(tlb_mr_ram_in),
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`endif
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`endif
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.doq(tlb_mr_ram_out)
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);
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);
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//
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//
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// Instantiation of ITLB Translate Registers
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// Instantiation of ITLB Translate Registers
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//
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//
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or1200_spram #
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or1200_spram #
|
(
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(
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.aw(6),
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.aw(6),
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`ifdef OR1200_RAM_PARITY
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.dw(24)
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`else
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.dw(22)
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.dw(22)
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`endif
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)
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)
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itlb_tr_ram
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itlb_tr_ram
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(
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(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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.mbist_si_i(itlb_tr_ram_si),
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.mbist_si_i(itlb_tr_ram_si),
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.mbist_so_o(itlb_tr_ram_so),
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.mbist_so_o(itlb_tr_ram_so),
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.mbist_ctrl_i(mbist_ctrl_i),
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.mbist_ctrl_i(mbist_ctrl_i),
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`endif
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`endif
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.ce(tlb_tr_en),
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.ce(tlb_tr_en),
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.we(tlb_tr_we),
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.we(tlb_tr_we),
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//.oe(1'b1),
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//.oe(1'b1),
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.addr(tlb_index),
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.addr(tlb_index),
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.di(tlb_tr_ram_in),
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.doq(tlb_tr_ram_out)
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`ifdef OR1200_RAM_PARITY
|
`ifdef OR1200_RAM_PARITY
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, .p_err()
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.p_err(p_err_wire[1]),
|
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.di({2'b00,tlb_tr_ram_in}),
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`else
|
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.di(tlb_tr_ram_in),
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`endif
|
`endif
|
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.doq(tlb_tr_ram_out)
|
);
|
);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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