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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's Instruction MMU top level ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// Description ////
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//// Instantiation of all IMMU blocks. ////
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//// ////
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//// To Do: ////
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//// - cache inhibit ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: or1200_immu_top.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Structure reordered and bugs fixed.
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//
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// Revision 1.15 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.14 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.12.4.2 2003/12/09 11:46:48 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.12.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.12 2003/06/06 02:54:47 lampret
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// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
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//
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// Revision 1.11 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.10 2002/09/16 03:08:56 lampret
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// Disabled cache inhibit atttribute.
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//
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// Revision 1.9 2002/08/18 19:54:17 lampret
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// Added store buffer.
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//
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// Revision 1.8 2002/08/14 06:23:50 lampret
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// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
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//
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// Revision 1.7 2002/08/12 05:31:30 lampret
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// Delayed external access at page crossing.
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//
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// Revision 1.6 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.4 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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//
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.6 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.5 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.1 2001/08/17 08:03:35 lampret
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// *** empty log message ***
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//
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// Revision 1.2 2001/07/22 03:31:53 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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//
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// Insn MMU
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//
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module or1200_immu_top(
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// Rst and clk
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clk, rst,
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// CPU i/f
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ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i,
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icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
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// SR Interface
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boot_adr_sel_i,
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// SPR access
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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`ifdef OR1200_BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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// QMEM i/f
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qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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//
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// I/O
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//
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//
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// Clock and reset
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//
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input clk;
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input rst;
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//
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// CPU I/F
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//
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input ic_en;
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input immu_en;
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input supv;
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input [aw-1:0] icpu_adr_i;
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input icpu_cycstb_i;
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output [aw-1:0] icpu_adr_o;
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output [3:0] icpu_tag_o;
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output icpu_rty_o;
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output icpu_err_o;
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//
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// SR Interface
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//
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input boot_adr_sel_i;
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//
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// SPR access
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//
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input spr_cs;
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input spr_write;
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input [aw-1:0] spr_addr;
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input [31:0] spr_dat_i;
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output [31:0] spr_dat_o;
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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`endif
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//
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// IC I/F
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//
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input qmemimmu_rty_i;
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input qmemimmu_err_i;
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input [3:0] qmemimmu_tag_i;
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output [aw-1:0] qmemimmu_adr_o;
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output qmemimmu_cycstb_o;
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output qmemimmu_ci_o;
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//
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// Internal wires and regs
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//
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wire itlb_spr_access;
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wire [31:`OR1200_IMMU_PS] itlb_ppn;
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wire itlb_hit;
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wire itlb_uxe;
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wire itlb_sxe;
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wire [31:0] itlb_dat_o;
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wire itlb_en;
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wire itlb_ci;
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wire itlb_done;
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wire fault;
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wire miss;
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wire page_cross;
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reg [31:0] icpu_adr_default;
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wire [31:0] icpu_adr_boot;
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reg icpu_adr_select;
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reg [31:0] icpu_adr_o;
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reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
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`ifdef OR1200_NO_IMMU
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`else
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reg itlb_en_r;
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reg dis_spr_access_frst_clk;
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reg dis_spr_access_scnd_clk;
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`endif
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//
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// Implemented bits inside match and translate registers
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//
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// itlbwYmrX: vpn 31-10 v 0
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// itlbwYtrX: ppn 31-10 uxe 7 sxe 6
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//
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// itlb memory width:
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// 19 bits for ppn
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// 13 bits for vpn
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// 1 bit for valid
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// 2 bits for protection
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// 1 bit for cache inhibit
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//
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// icpu_adr_o
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//
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(`OR1200_RST_EVENT rst or posedge clk)
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// default value
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if (rst == `OR1200_RST_VALUE) begin
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icpu_adr_default <= 32'h0000_0100;
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icpu_adr_select <= 1'b1; // select async. value due to reset state
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end
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// selected value (different from default) is written into FF after reset state
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else if (icpu_adr_select) begin
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icpu_adr_default <= icpu_adr_boot; // dynamic value can only be assigned to FF out of reset!
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icpu_adr_select <= 1'b0; // select FF value
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end
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else begin
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icpu_adr_default <= icpu_adr_i;
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end
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// select async. value for boot address after reset - PC jumps to the address selected after boot!
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//assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), 12'h100} ;
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assign icpu_adr_boot = `OR1200_BOOT_ADR; // jb
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always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
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if (icpu_adr_select)
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icpu_adr_o = icpu_adr_boot ; // async. value is selected due to reset state
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else
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icpu_adr_o = icpu_adr_default ; // FF value is selected 2nd clock after reset state
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`else
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Unsupported !!!
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`endif
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//
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// Page cross
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//
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// Asserted when CPU address crosses page boundary. Most of the time it is zero.
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//
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assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
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//
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// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
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// one clock cycle after offset part.
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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icpu_vpn_r <= {32-`OR1200_IMMU_PS{1'b0}};
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else
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icpu_vpn_r <= icpu_adr_i[31:`OR1200_IMMU_PS];
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`ifdef OR1200_NO_IMMU
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//
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// Put all outputs in inactive state
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//
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assign spr_dat_o = 32'h00000000;
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assign qmemimmu_adr_o = icpu_adr_i;
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assign icpu_tag_o = qmemimmu_tag_i;
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assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
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assign icpu_rty_o = qmemimmu_rty_i;
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assign icpu_err_o = qmemimmu_err_i;
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assign qmemimmu_ci_o = `OR1200_IMMU_CI;
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`ifdef OR1200_BIST
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assign mbist_so_o = mbist_si_i;
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`endif
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`else
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//
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// ITLB SPR access
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//
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// 1200 - 12FF itlbmr w0
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// 1200 - 123F itlbmr w0 [63:0]
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//
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// 1300 - 13FF itlbtr w0
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// 1300 - 133F itlbtr w0 [63:0]
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//
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assign itlb_spr_access = spr_cs & ~dis_spr_access_scnd_clk;
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//
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// Disable ITLB SPR access
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//
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// This flops are used to mask ITLB miss/fault exception
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// during first & second clock cycles of accessing ITLB SPR. In
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// subsequent clock cycles it is assumed that ITLB SPR
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// access was accomplished and that normal instruction fetching
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// can proceed.
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//
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// spr_cs sets dis_spr_access_frst_clk and icpu_rty_o clears it.
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// dis_spr_access_frst_clk sets dis_spr_access_scnd_clk and
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// icpu_rty_o clears it.
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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dis_spr_access_frst_clk <= 1'b0;
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else if (!icpu_rty_o)
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dis_spr_access_frst_clk <= 1'b0;
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else if (spr_cs)
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dis_spr_access_frst_clk <= 1'b1;
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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dis_spr_access_scnd_clk <= 1'b0;
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else if (!icpu_rty_o)
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dis_spr_access_scnd_clk <= 1'b0;
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else if (dis_spr_access_frst_clk)
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dis_spr_access_scnd_clk <= 1'b1;
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//
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// Tags:
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//
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// OR1200_ITAG_TE - TLB miss Exception
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// OR1200_ITAG_PE - Page fault Exception
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//
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assign icpu_tag_o = miss ? `OR1200_ITAG_TE : fault ? `OR1200_ITAG_PE : qmemimmu_tag_i;
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//
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// icpu_rty_o
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//
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// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
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//assign icpu_rty_o = qmemimmu_rty_i | itlb_spr_access & immu_en;
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assign icpu_rty_o = qmemimmu_rty_i;
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//
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// icpu_err_o
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//
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assign icpu_err_o = miss | fault | qmemimmu_err_i;
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//
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// Assert itlb_en_r after one clock cycle and when there is no
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// ITLB SPR access
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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itlb_en_r <= 1'b0;
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else
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itlb_en_r <= itlb_en & ~itlb_spr_access;
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//
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// ITLB lookup successful
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//
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assign itlb_done = itlb_en_r & ~page_cross;
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//
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// Cut transfer when access (mtspr/mfspr) to/from ITLB occure or if something goes
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// wrong with translation. If IC is disabled, use delayed signals.
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//
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// assign qmemimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
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//assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
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assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done & ~itlb_spr_access : icpu_cycstb_i & ~page_cross;
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//
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// Cache Inhibit
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//
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// Cache inhibit is not really needed for instruction memory subsystem.
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// If we would doq it, we would doq it like this.
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// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
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// However this causes an async combinatorial loop so we stick to
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// no cache inhibit.
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//assign qmemimmu_ci_o = `OR1200_IMMU_CI;
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// Cache inhibit without an async combinatorial loop
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assign qmemimmu_ci_o = immu_en ? itlb_ci : `OR1200_IMMU_CI;
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//
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// Physical address is either translated virtual address or
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// simply equal when IMMU is disabled
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//
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//assign qmemimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
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assign qmemimmu_adr_o = immu_en & itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0};
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reg [31:0] spr_dat_reg;
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//
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// Output to SPRS unit
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//
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// spr_dat_o is registered on the 1st clock of spr read
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// so itlb can continue with process during execution of mfspr.
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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spr_dat_reg <= 32'h0000_0000;
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else if (spr_cs & !dis_spr_access_scnd_clk)
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spr_dat_reg <= itlb_dat_o;
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assign spr_dat_o = itlb_spr_access ? itlb_dat_o : spr_dat_reg;
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//
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// Page fault exception logic
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//
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assign fault = itlb_done &
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( (!supv & !itlb_uxe) // Execute in user mode not enabled
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|| (supv & !itlb_sxe)); // Execute in supv mode not enabled
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//
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// TLB Miss exception logic
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//
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assign miss = itlb_done & !itlb_hit;
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//
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// ITLB Enable
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//
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assign itlb_en = immu_en & icpu_cycstb_i;
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//
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// Instantiation of ITLB
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//
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or1200_immu_tlb or1200_immu_tlb(
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// Rst and clk
|
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.clk(clk),
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.rst(rst),
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|
|
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// I/F for translation
|
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.tlb_en(itlb_en),
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.vaddr(icpu_adr_i),
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.hit(itlb_hit),
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.ppn(itlb_ppn),
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.uxe(itlb_uxe),
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.sxe(itlb_sxe),
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.ci(itlb_ci),
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|
|
`ifdef OR1200_BIST
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|
// RAM BIST
|
|
.mbist_si_i(mbist_si_i),
|
|
.mbist_so_o(mbist_so_o),
|
|
.mbist_ctrl_i(mbist_ctrl_i),
|
|
`endif
|
|
|
|
// SPR access
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|
.spr_cs(itlb_spr_access),
|
|
.spr_write(spr_write),
|
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.spr_addr(spr_addr),
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|
.spr_dat_i(spr_dat_i),
|
|
.spr_dat_o(itlb_dat_o)
|
|
);
|
|
|
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`endif
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|
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endmodule
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No newline at end of file
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