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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Instruction MMU top level ////
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//// OR1200's Instruction MMU top level ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Instantiation of all IMMU blocks. ////
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//// Instantiation of all IMMU blocks. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: or1200_immu_top.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Structure reordered and bugs fixed.
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//
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// Revision 1.15 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.14 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.12.4.2 2003/12/09 11:46:48 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.12.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.12 2003/06/06 02:54:47 lampret
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// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
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//
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// Revision 1.11 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.10 2002/09/16 03:08:56 lampret
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// Disabled cache inhibit atttribute.
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//
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// Revision 1.9 2002/08/18 19:54:17 lampret
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// Added store buffer.
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//
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// Revision 1.8 2002/08/14 06:23:50 lampret
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// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
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//
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// Revision 1.7 2002/08/12 05:31:30 lampret
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// Delayed external access at page crossing.
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//
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// Revision 1.6 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.4 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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//
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.6 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.5 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.1 2001/08/17 08:03:35 lampret
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// *** empty log message ***
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//
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// Revision 1.2 2001/07/22 03:31:53 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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//
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//
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(`OR1200_RST_EVENT rst or posedge clk)
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always @(`OR1200_RST_EVENT rst or posedge clk)
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// default value
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// default value
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if (rst == `OR1200_RST_VALUE) begin
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if (rst == `OR1200_RST_VALUE) begin
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// select async. value due to reset state
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icpu_adr_default <= 32'h0000_0100;
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icpu_adr_default <= 32'h0000_0100;
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icpu_adr_select <= 1'b1; // select async. value due to reset state
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icpu_adr_select <= 1'b1;
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end
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end
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// selected value (different from default) is written into FF after reset state
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// selected value (different from default) is written
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// into FF after reset state
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else if (icpu_adr_select) begin
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else if (icpu_adr_select) begin
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icpu_adr_default <= icpu_adr_boot; // dynamic value can only be assigned to FF out of reset!
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// dynamic value can only be assigned to FF out of reset!
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icpu_adr_select <= 1'b0; // select FF value
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icpu_adr_default <= icpu_adr_boot;
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// select FF value
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icpu_adr_select <= 1'b0;
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end
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end
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else begin
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else begin
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icpu_adr_default <= icpu_adr_i;
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icpu_adr_default <= icpu_adr_i;
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end
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end
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// select async. value for boot address after reset - PC jumps to the address selected after boot!
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// select async. value for boot address after reset - PC jumps to the address
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//assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), 12'h100} ;
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// selected after boot!
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//assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P :
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// `OR1200_EXCEPT_EPH0_P), 12'h100} ;
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assign icpu_adr_boot = `OR1200_BOOT_ADR; // jb
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assign icpu_adr_boot = `OR1200_BOOT_ADR; // jb
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always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
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always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
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if (icpu_adr_select)
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if (icpu_adr_select)
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icpu_adr_o = icpu_adr_boot ; // async. value is selected due to reset state
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// async. value is selected due to reset state
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icpu_adr_o = icpu_adr_boot ;
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else
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else
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icpu_adr_o = icpu_adr_default ; // FF value is selected 2nd clock after reset state
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// FF value is selected 2nd clock after reset state
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icpu_adr_o = icpu_adr_default ;
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`else
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`else
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Unsupported !!!
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Unsupported !!!
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`endif
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`endif
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//
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//
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