| Line 67... |
Line 67... |
`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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// Parity error indicator
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p_err,
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`endif
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// QMEM i/f
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// QMEM i/f
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qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
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qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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| Line 120... |
Line 125... |
input mbist_si_i;
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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output mbist_so_o;
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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output [1:0] p_err;
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`endif
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//
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//
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// IC I/F
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// IC I/F
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//
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//
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input qmemimmu_rty_i;
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input qmemimmu_rty_i;
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input qmemimmu_err_i;
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input qmemimmu_err_i;
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| Line 156... |
Line 165... |
`else
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`else
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reg itlb_en_r;
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reg itlb_en_r;
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reg dis_spr_access_frst_clk;
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reg dis_spr_access_frst_clk;
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reg dis_spr_access_scnd_clk;
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reg dis_spr_access_scnd_clk;
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`endif
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`endif
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reg [31:0] spr_dat_reg;
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//
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//
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// Implemented bits inside match and translate registers
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// Implemented bits inside match and translate registers
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//
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//
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// itlbwYmrX: vpn 31-10 v 0
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// itlbwYmrX: vpn 31-10 v 0
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| Line 170... |
Line 180... |
// 13 bits for vpn
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// 13 bits for vpn
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// 1 bit for valid
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// 1 bit for valid
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// 2 bits for protection
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// 2 bits for protection
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// 1 bit for cache inhibit
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// 1 bit for cache inhibit
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assign icpu_adr_boot = `OR1200_BOOT_ADR;
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//
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//
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// icpu_adr_o
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// icpu_adr_o
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//
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//
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(`OR1200_RST_EVENT rst or posedge clk)
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always @(`OR1200_RST_EVENT rst or posedge clk)
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// default value
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// default value
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if (rst == `OR1200_RST_VALUE) begin
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if (rst == `OR1200_RST_VALUE) begin
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// select async. value due to reset state
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// select async. value due to reset state
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icpu_adr_default <= 32'h0000_0100;
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icpu_adr_o <= 32'h0000_0100;
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icpu_adr_select <= 1'b1;
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icpu_adr_select <= 1'b1;
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end
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end
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// selected value (different from default) is written
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// selected value (different from default) is written
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// into FF after reset state
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// into FF after reset state
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else if (icpu_adr_select) begin
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else if (icpu_adr_select) begin
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// dynamic value can only be assigned to FF out of reset!
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// dynamic value can only be assigned to FF out of reset!
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icpu_adr_default <= icpu_adr_boot;
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icpu_adr_o <= icpu_adr_boot;
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// select FF value
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// select FF value
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icpu_adr_select <= 1'b0;
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icpu_adr_select <= 1'b0;
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end
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end
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else begin
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else begin
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icpu_adr_default <= icpu_adr_i;
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icpu_adr_o <= icpu_adr_i;
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end
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end
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// select async. value for boot address after reset - PC jumps to the address
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// selected after boot!
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//assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P :
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// `OR1200_EXCEPT_EPH0_P), 12'h100} ;
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assign icpu_adr_boot = `OR1200_BOOT_ADR; // jb
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always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
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if (icpu_adr_select)
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// async. value is selected due to reset state
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icpu_adr_o = icpu_adr_boot ;
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else
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// FF value is selected 2nd clock after reset state
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icpu_adr_o = icpu_adr_default ;
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`else
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`else
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Unsupported !!!
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Unsupported !!!
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`endif
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`endif
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//
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//
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| Line 218... |
Line 217... |
// Asserted when CPU address crosses page boundary. Most of the time it is zero.
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// Asserted when CPU address crosses page boundary. Most of the time it is zero.
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//
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//
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assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
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assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
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//
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//
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// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
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// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is
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// one clock cycle after offset part.
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// expected to come one clock cycle after offset part.
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//
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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if (rst == `OR1200_RST_VALUE)
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icpu_vpn_r <= {32-`OR1200_IMMU_PS{1'b0}};
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icpu_vpn_r <= {32-`OR1200_IMMU_PS{1'b0}};
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else
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else
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| Line 242... |
Line 241... |
assign icpu_err_o = qmemimmu_err_i;
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assign icpu_err_o = qmemimmu_err_i;
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assign qmemimmu_ci_o = `OR1200_IMMU_CI;
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assign qmemimmu_ci_o = `OR1200_IMMU_CI;
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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assign mbist_so_o = mbist_si_i;
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assign mbist_so_o = mbist_si_i;
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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assign p_err = 0;
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`endif
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`else
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`else
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//
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//
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// ITLB SPR access
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// ITLB SPR access
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//
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//
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| Line 290... |
Line 293... |
// Tags:
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// Tags:
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//
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//
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// OR1200_ITAG_TE - TLB miss Exception
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// OR1200_ITAG_TE - TLB miss Exception
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// OR1200_ITAG_PE - Page fault Exception
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// OR1200_ITAG_PE - Page fault Exception
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//
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//
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assign icpu_tag_o = miss ? `OR1200_ITAG_TE : fault ? `OR1200_ITAG_PE : qmemimmu_tag_i;
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assign icpu_tag_o = miss ? `OR1200_ITAG_TE :
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fault ? `OR1200_ITAG_PE : qmemimmu_tag_i;
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//
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//
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// icpu_rty_o
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// icpu_rty_o
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//
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//
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// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
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// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
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| Line 302... |
Line 306... |
assign icpu_rty_o = qmemimmu_rty_i;
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assign icpu_rty_o = qmemimmu_rty_i;
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//
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//
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// icpu_err_o
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// icpu_err_o
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//
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//
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assign icpu_err_o = miss | fault | qmemimmu_err_i;
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assign icpu_err_o = miss | fault | qmemimmu_err_i
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`ifdef OR1200_RAM_PARITY
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| (|p_err)
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`endif
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;
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//
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//
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// Assert itlb_en_r after one clock cycle and when there is no
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// Assert itlb_en_r after one clock cycle and when there is no
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// ITLB SPR access
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// ITLB SPR access
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//
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//
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| Line 320... |
Line 328... |
// ITLB lookup successful
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// ITLB lookup successful
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//
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//
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assign itlb_done = itlb_en_r & ~page_cross;
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assign itlb_done = itlb_en_r & ~page_cross;
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//
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//
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// Cut transfer when access (mtspr/mfspr) to/from ITLB occure or if something goes
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// Cut transfer when access (mtspr/mfspr) to/from ITLB occurs or if something
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// wrong with translation. If IC is disabled, use delayed signals.
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// goes wrong with translation. If IC is disabled, use delayed signals.
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//
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//
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// assign qmemimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
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assign qmemimmu_cycstb_o = immu_en ?
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//assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
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~(miss | fault) & icpu_cycstb_i & ~page_cross &
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assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done & ~itlb_spr_access : icpu_cycstb_i & ~page_cross;
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itlb_done & ~itlb_spr_access :
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icpu_cycstb_i & ~page_cross;
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//
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//
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// Cache Inhibit
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// Cache Inhibit
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//
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//
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// Cache inhibit is not really needed for instruction memory subsystem.
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// Cache inhibit is not really needed for instruction memory subsystem.
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// If we would doq it, we would doq it like this.
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// If we would doq it, we would doq it like this.
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// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
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// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
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// However this causes an async combinatorial loop so we stick to
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// However this causes an async combinatorial loop so we stick to
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// no cache inhibit.
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// no cache inhibit.
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//assign qmemimmu_ci_o = `OR1200_IMMU_CI;
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// Cache inhibit without an async combinatorial loop
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assign qmemimmu_ci_o = immu_en ? itlb_ci : `OR1200_IMMU_CI;
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assign qmemimmu_ci_o = immu_en ? itlb_ci : `OR1200_IMMU_CI;
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|
|
|
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//
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//
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// Physical address is either translated virtual address or
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// Physical address is either translated virtual address or
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// simply equal when IMMU is disabled
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// simply equal when IMMU is disabled
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//
|
//
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//assign qmemimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
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assign qmemimmu_adr_o = immu_en & itlb_done ?
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assign qmemimmu_adr_o = immu_en & itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0};
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{itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0} :
|
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{icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0};
|
|
|
reg [31:0] spr_dat_reg;
|
|
//
|
//
|
// Output to SPRS unit
|
// Output to SPRS unit
|
//
|
//
|
// spr_dat_o is registered on the 1st clock of spr read
|
// spr_dat_o is registered on the 1st clock of spr read
|
// so itlb can continue with process during execution of mfspr.
|
// so itlb can continue with process during execution of mfspr.
|
| Line 366... |
Line 373... |
//
|
//
|
// Page fault exception logic
|
// Page fault exception logic
|
//
|
//
|
assign fault = itlb_done &
|
assign fault = itlb_done &
|
( (!supv & !itlb_uxe) // Execute in user mode not enabled
|
( (!supv & !itlb_uxe) // Execute in user mode not enabled
|
|| (supv & !itlb_sxe)); // Execute in supv mode not enabled
|
|| (supv & !itlb_sxe));// Execute in supv mode not en.
|
|
|
//
|
//
|
// TLB Miss exception logic
|
// TLB Miss exception logic
|
//
|
//
|
assign miss = itlb_done & !itlb_hit;
|
assign miss = itlb_done & !itlb_hit;
|
| Line 402... |
Line 409... |
.mbist_si_i(mbist_si_i),
|
.mbist_si_i(mbist_si_i),
|
.mbist_so_o(mbist_so_o),
|
.mbist_so_o(mbist_so_o),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
.mbist_ctrl_i(mbist_ctrl_i),
|
`endif
|
`endif
|
|
|
|
`ifdef OR1200_RAM_PARITY
|
|
.p_err(p_err),
|
|
`endif
|
|
|
// SPR access
|
// SPR access
|
.spr_cs(itlb_spr_access),
|
.spr_cs(itlb_spr_access),
|
.spr_write(spr_write),
|
.spr_write(spr_write),
|
.spr_addr(spr_addr),
|
.spr_addr(spr_addr),
|
.spr_dat_i(spr_dat_i),
|
.spr_dat_i(spr_dat_i),
|
