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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's mem2reg alignment ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// Description ////
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//// Two versions of Memory to register data alignment. ////
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//// ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: or1200_mem2reg.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// No update
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//
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// Revision 1.5 2002/09/03 22:28:21 lampret
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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//
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// Revision 1.4 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.3 2002/03/28 19:14:10 lampret
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// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.8 2001/10/19 23:28:46 lampret
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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//
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_mem2reg(addr, lsu_op, memdata, regdata);
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parameter width = `OR1200_OPERAND_WIDTH;
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//
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// I/O
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//
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input [1:0] addr;
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input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
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input [width-1:0] memdata;
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output [width-1:0] regdata;
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//
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// In the past faster implementation of mem2reg (today probably slower)
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//
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`ifdef OR1200_IMPL_MEM2REG2
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`define OR1200_M2R_BYTE0 4'b0000
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`define OR1200_M2R_BYTE1 4'b0001
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`define OR1200_M2R_BYTE2 4'b0010
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`define OR1200_M2R_BYTE3 4'b0011
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`define OR1200_M2R_EXTB0 4'b0100
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`define OR1200_M2R_EXTB1 4'b0101
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`define OR1200_M2R_EXTB2 4'b0110
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`define OR1200_M2R_EXTB3 4'b0111
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`define OR1200_M2R_ZERO 4'b0000
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reg [7:0] regdata_hh;
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reg [7:0] regdata_hl;
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reg [7:0] regdata_lh;
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reg [7:0] regdata_ll;
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reg [width-1:0] aligned;
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reg [3:0] sel_byte0, sel_byte1,
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sel_byte2, sel_byte3;
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assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};
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//
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// Byte select 0
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//
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always @(addr or lsu_op) begin
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casex({lsu_op[2:0], addr}) // synopsys parallel_case
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{3'b01x, 2'b00}: // lbz/lbs 0
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sel_byte0 = `OR1200_M2R_BYTE3; // take byte 3
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{3'b01x, 2'b01}, // lbz/lbs 1
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{3'b10x, 2'b00}: // lhz/lhs 0
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sel_byte0 = `OR1200_M2R_BYTE2; // take byte 2
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{3'b01x, 2'b10}: // lbz/lbs 2
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sel_byte0 = `OR1200_M2R_BYTE1; // take byte 1
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default: // all other cases
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sel_byte0 = `OR1200_M2R_BYTE0; // take byte 0
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endcase
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end
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//
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// Byte select 1
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//
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always @(addr or lsu_op) begin
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casex({lsu_op[2:0], addr}) // synopsys parallel_case
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{3'b010, 2'bxx}: // lbz
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sel_byte1 = `OR1200_M2R_ZERO; // zero extend
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{3'b011, 2'b00}: // lbs 0
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sel_byte1 = `OR1200_M2R_EXTB3; // sign extend from byte 3
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{3'b011, 2'b01}: // lbs 1
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sel_byte1 = `OR1200_M2R_EXTB2; // sign extend from byte 2
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{3'b011, 2'b10}: // lbs 2
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sel_byte1 = `OR1200_M2R_EXTB1; // sign extend from byte 1
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{3'b011, 2'b11}: // lbs 3
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sel_byte1 = `OR1200_M2R_EXTB0; // sign extend from byte 0
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{3'b10x, 2'b00}: // lhz/lhs 0
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sel_byte1 = `OR1200_M2R_BYTE3; // take byte 3
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default: // all other cases
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sel_byte1 = `OR1200_M2R_BYTE1; // take byte 1
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endcase
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end
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//
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// Byte select 2
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//
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always @(addr or lsu_op) begin
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casex({lsu_op[2:0], addr}) // synopsys parallel_case
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{3'b010, 2'bxx}, // lbz
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{3'b100, 2'bxx}: // lhz
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sel_byte2 = `OR1200_M2R_ZERO; // zero extend
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{3'b011, 2'b00}, // lbs 0
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{3'b101, 2'b00}: // lhs 0
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sel_byte2 = `OR1200_M2R_EXTB3; // sign extend from byte 3
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{3'b011, 2'b01}: // lbs 1
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sel_byte2 = `OR1200_M2R_EXTB2; // sign extend from byte 2
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{3'b011, 2'b10}, // lbs 2
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{3'b101, 2'b10}: // lhs 0
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sel_byte2 = `OR1200_M2R_EXTB1; // sign extend from byte 1
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{3'b011, 2'b11}: // lbs 3
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sel_byte2 = `OR1200_M2R_EXTB0; // sign extend from byte 0
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default: // all other cases
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sel_byte2 = `OR1200_M2R_BYTE2; // take byte 2
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endcase
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end
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//
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// Byte select 3
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//
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always @(addr or lsu_op) begin
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casex({lsu_op[2:0], addr}) // synopsys parallel_case
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{3'b010, 2'bxx}, // lbz
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{3'b100, 2'bxx}: // lhz
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sel_byte3 = `OR1200_M2R_ZERO; // zero extend
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{3'b011, 2'b00}, // lbs 0
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{3'b101, 2'b00}: // lhs 0
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sel_byte3 = `OR1200_M2R_EXTB3; // sign extend from byte 3
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{3'b011, 2'b01}: // lbs 1
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sel_byte3 = `OR1200_M2R_EXTB2; // sign extend from byte 2
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{3'b011, 2'b10}, // lbs 2
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{3'b101, 2'b10}: // lhs 0
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sel_byte3 = `OR1200_M2R_EXTB1; // sign extend from byte 1
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{3'b011, 2'b11}: // lbs 3
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sel_byte3 = `OR1200_M2R_EXTB0; // sign extend from byte 0
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default: // all other cases
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sel_byte3 = `OR1200_M2R_BYTE3; // take byte 3
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endcase
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end
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//
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// Byte 0
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//
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always @(sel_byte0 or memdata) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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`ifdef OR1200_CASE_DEFAULT
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case(sel_byte0) // synopsys parallel_case infer_mux
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`else
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case(sel_byte0) // synopsys full_case parallel_case infer_mux
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`endif
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`else
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`ifdef OR1200_CASE_DEFAULT
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case(sel_byte0) // synopsys parallel_case
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`else
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case(sel_byte0) // synopsys full_case parallel_case
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`endif
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`endif
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`OR1200_M2R_BYTE0: begin
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regdata_ll = memdata[7:0];
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end
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`OR1200_M2R_BYTE1: begin
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regdata_ll = memdata[15:8];
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end
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`OR1200_M2R_BYTE2: begin
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regdata_ll = memdata[23:16];
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end
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`ifdef OR1200_CASE_DEFAULT
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default: begin
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`else
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`OR1200_M2R_BYTE3: begin
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`endif
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regdata_ll = memdata[31:24];
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end
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endcase
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end
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//
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// Byte 1
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//
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always @(sel_byte1 or memdata) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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`ifdef OR1200_CASE_DEFAULT
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case(sel_byte1) // synopsys parallel_case infer_mux
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`else
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case(sel_byte1) // synopsys full_case parallel_case infer_mux
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`endif
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`else
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`ifdef OR1200_CASE_DEFAULT
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case(sel_byte1) // synopsys parallel_case
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`else
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case(sel_byte1) // synopsys full_case parallel_case
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`endif
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`endif
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`OR1200_M2R_ZERO: begin
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regdata_lh = 8'h00;
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end
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`OR1200_M2R_BYTE1: begin
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regdata_lh = memdata[15:8];
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end
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`OR1200_M2R_BYTE3: begin
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regdata_lh = memdata[31:24];
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end
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`OR1200_M2R_EXTB0: begin
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regdata_lh = {8{memdata[7]}};
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end
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`OR1200_M2R_EXTB1: begin
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regdata_lh = {8{memdata[15]}};
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end
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`OR1200_M2R_EXTB2: begin
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regdata_lh = {8{memdata[23]}};
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end
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`ifdef OR1200_CASE_DEFAULT
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default: begin
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`else
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`OR1200_M2R_EXTB3: begin
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`endif
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regdata_lh = {8{memdata[31]}};
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end
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endcase
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end
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//
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// Byte 2
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//
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always @(sel_byte2 or memdata) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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`ifdef OR1200_CASE_DEFAULT
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case(sel_byte2) // synopsys parallel_case infer_mux
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`else
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case(sel_byte2) // synopsys full_case parallel_case infer_mux
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`endif
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`else
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`ifdef OR1200_CASE_DEFAULT
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case(sel_byte2) // synopsys parallel_case
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`else
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case(sel_byte2) // synopsys full_case parallel_case
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`endif
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`endif
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`OR1200_M2R_ZERO: begin
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regdata_hl = 8'h00;
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end
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`OR1200_M2R_BYTE2: begin
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regdata_hl = memdata[23:16];
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end
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`OR1200_M2R_EXTB0: begin
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regdata_hl = {8{memdata[7]}};
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end
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`OR1200_M2R_EXTB1: begin
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regdata_hl = {8{memdata[15]}};
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end
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`OR1200_M2R_EXTB2: begin
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regdata_hl = {8{memdata[23]}};
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end
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`ifdef OR1200_CASE_DEFAULT
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default: begin
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`else
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`OR1200_M2R_EXTB3: begin
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`endif
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regdata_hl = {8{memdata[31]}};
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end
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endcase
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end
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//
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// Byte 3
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//
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always @(sel_byte3 or memdata) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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`ifdef OR1200_CASE_DEFAULT
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case(sel_byte3) // synopsys parallel_case infer_mux
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`else
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case(sel_byte3) // synopsys full_case parallel_case infer_mux
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`endif
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`else
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`ifdef OR1200_CASE_DEFAULT
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case(sel_byte3) // synopsys parallel_case
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`else
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case(sel_byte3) // synopsys full_case parallel_case
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`endif
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`endif
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`OR1200_M2R_ZERO: begin
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regdata_hh = 8'h00;
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end
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`OR1200_M2R_BYTE3: begin
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regdata_hh = memdata[31:24];
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end
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`OR1200_M2R_EXTB0: begin
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regdata_hh = {8{memdata[7]}};
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end
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`OR1200_M2R_EXTB1: begin
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regdata_hh = {8{memdata[15]}};
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end
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`OR1200_M2R_EXTB2: begin
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regdata_hh = {8{memdata[23]}};
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end
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`ifdef OR1200_CASE_DEFAULT
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`OR1200_M2R_EXTB3: begin
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`else
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`OR1200_M2R_EXTB3: begin
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`endif
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regdata_hh = {8{memdata[31]}};
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end
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endcase
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end
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`else
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//
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// Straightforward implementation of mem2reg
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//
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reg [width-1:0] regdata;
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reg [width-1:0] aligned;
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//
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// Alignment
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//
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always @(addr or memdata) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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case(addr) // synopsys parallel_case infer_mux
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`else
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case(addr) // synopsys parallel_case
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`endif
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2'b00:
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aligned = memdata;
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2'b01:
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aligned = {memdata[23:0], 8'b0};
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2'b10:
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aligned = {memdata[15:0], 16'b0};
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2'b11:
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aligned = {memdata[7:0], 24'b0};
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endcase
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end
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//
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// Bytes
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//
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always @(lsu_op or aligned) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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case(lsu_op) // synopsys parallel_case infer_mux
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`else
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case(lsu_op) // synopsys parallel_case
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`endif
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`OR1200_LSUOP_LBZ: begin
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regdata[7:0] = aligned[31:24];
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regdata[31:8] = 24'b0;
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end
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`OR1200_LSUOP_LBS: begin
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regdata[7:0] = aligned[31:24];
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regdata[31:8] = {24{aligned[31]}};
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end
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`OR1200_LSUOP_LHZ: begin
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regdata[15:0] = aligned[31:16];
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regdata[31:16] = 16'b0;
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end
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`OR1200_LSUOP_LHS: begin
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regdata[15:0] = aligned[31:16];
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regdata[31:16] = {16{aligned[31]}};
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end
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default:
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regdata = aligned;
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endcase
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end
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`endif
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endmodule
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No newline at end of file
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No newline at end of file
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