| Line 63... |
Line 63... |
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// Multiplier/MAC interface
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// Multiplier/MAC interface
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ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op,
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ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op,
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result, mult_mac_stall,
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result, mult_mac_stall,
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// Overflow
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ovforw, ov_we,
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// SPR interface
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// SPR interface
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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);
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);
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parameter width = `OR1200_OPERAND_WIDTH;
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parameter width = `OR1200_OPERAND_WIDTH;
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| Line 91... |
Line 94... |
input [width-1:0] b;
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input [width-1:0] b;
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input [`OR1200_MACOP_WIDTH-1:0] mac_op;
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input [`OR1200_MACOP_WIDTH-1:0] mac_op;
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input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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output [width-1:0] result;
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output [width-1:0] result;
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output mult_mac_stall;
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output mult_mac_stall;
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output ovforw, ov_we;
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//
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//
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// SPR interface
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// SPR interface
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//
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//
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input spr_cs;
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input spr_cs;
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| Line 153... |
Line 157... |
reg [5:0] div_cntr;
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reg [5:0] div_cntr;
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`else
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`else
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reg [width-1:0] div_quot_r;
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reg [width-1:0] div_quot_r;
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reg [width-1:0] div_quot_generic;
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reg [width-1:0] div_quot_generic;
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`endif
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`endif
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wire div_by_zero;
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`endif
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`endif
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reg ovforw, ov_we;
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//
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//
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// Combinatorial logic
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// Combinatorial logic
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//
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//
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`ifdef OR1200_MULT_IMPLEMENTED
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`ifdef OR1200_MULT_IMPLEMENTED
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| Line 187... |
Line 193... |
assign x = (alu_op_sdiv | alu_op_smul) & a[31] ? ~a + 32'b1 :
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assign x = (alu_op_sdiv | alu_op_smul) & a[31] ? ~a + 32'b1 :
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alu_op_div | alu_op_mul | (|mac_op) ? a : 32'd0;
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alu_op_div | alu_op_mul | (|mac_op) ? a : 32'd0;
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assign y = (alu_op_sdiv | alu_op_smul) & b[31] ? ~b + 32'b1 :
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assign y = (alu_op_sdiv | alu_op_smul) & b[31] ? ~b + 32'b1 :
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alu_op_div | alu_op_mul | (|mac_op) ? b : 32'd0;
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alu_op_div | alu_op_mul | (|mac_op) ? b : 32'd0;
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assign div_by_zero = !(|b) & alu_op_div;
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// Used to indicate when we should check for new multiply or MAC ops
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// Used to indicate when we should check for new multiply or MAC ops
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always @(posedge clk or `OR1200_RST_EVENT rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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if (rst == `OR1200_RST_VALUE)
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ex_freeze_r <= 1'b1;
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ex_freeze_r <= 1'b1;
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else
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else
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| Line 226... |
Line 235... |
result = mac_r[31:0];
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result = mac_r[31:0];
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`endif
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`endif
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`else
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`else
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result = {width{1'b0}};
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result = {width{1'b0}};
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`endif
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`endif
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endcase
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endcase // casez (alu_op)
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//
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// Overflow generation
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//
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always @*
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casez(alu_op) // synopsys parallel_case
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`ifdef OR1200_IMPL_OV
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`ifdef OR1200_MULT_IMPLEMENTED
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`OR1200_ALUOP_MUL: begin
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// Actually doing unsigned multiply internally, and then negate on
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// output as appropriate, so if sign bit is set, then is overflow
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ovforw = mul_prod_r[31];
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ov_we = 1;
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end
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`OR1200_ALUOP_MULU : begin
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// Overflow on unsigned multiply is simpler.
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ovforw = mul_prod_r[32];
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ov_we = 1;
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end
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`endif // `ifdef OR1200_MULT_IMPLEMENTED
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`ifdef OR1200_DIV_IMPLEMENTED
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`OR1200_ALUOP_DIVU,
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`OR1200_ALUOP_DIV: begin
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// Overflow on divide by zero
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ovforw = div_by_zero;
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ov_we = 1;
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end
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`endif
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`endif // `ifdef OR1200_IMPL_OV
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default: begin
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ovforw = 0;
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ov_we = 0;
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end
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endcase // casez (alu_op)
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|
|
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`ifdef OR1200_MULT_IMPLEMENTED
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`ifdef OR1200_MULT_IMPLEMENTED
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`ifdef OR1200_MULT_SERIAL
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`ifdef OR1200_MULT_SERIAL
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|
|
always @(`OR1200_RST_EVENT rst or posedge clk)
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always @(`OR1200_RST_EVENT rst or posedge clk)
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| Line 396... |
Line 441... |
if (rst == `OR1200_RST_VALUE) begin
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if (rst == `OR1200_RST_VALUE) begin
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div_quot_r <= 64'h0000_0000_0000_0000;
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div_quot_r <= 64'h0000_0000_0000_0000;
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div_free <= 1'b1;
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div_free <= 1'b1;
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div_cntr <= 6'b00_0000;
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div_cntr <= 6'b00_0000;
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end
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end
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else if (div_by_zero) begin
|
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div_quot_r <= 64'h0000_0000_0000_0000;
|
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div_free <= 1'b1;
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div_cntr <= 6'b00_0000;
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end
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else if (|div_cntr) begin
|
else if (|div_cntr) begin
|
if (div_tmp[31])
|
if (div_tmp[31])
|
div_quot_r <= {div_quot_r[62:0], 1'b0};
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div_quot_r <= {div_quot_r[62:0], 1'b0};
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else
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else
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div_quot_r <= {div_tmp[30:0], div_quot_r[31:0], 1'b1};
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div_quot_r <= {div_tmp[30:0], div_quot_r[31:0], 1'b1};
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