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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_mult_mac.v] - Diff between revs 502 and 505

Rev 502	Rev 505
Line 248...	Line 248...
`ifdef OR1200_IMPL_OV	`ifdef OR1200_IMPL_OV
`ifdef OR1200_MULT_IMPLEMENTED	`ifdef OR1200_MULT_IMPLEMENTED
`OR1200_ALUOP_MUL: begin	`OR1200_ALUOP_MUL: begin
`// Actually doing unsigned multiply internally, and then negate on`	`// Actually doing unsigned multiply internally, and then negate on`
`// output as appropriate, so if sign bit is set, then is overflow`	`// output as appropriate, so if sign bit is set, then is overflow`
`ovforw = mul_prod_r[31];`	`// unless incoming signs differ and result is 2^(width-1)`
	`ovforw = (mul_prod_r[width-1] &&`
	`!((a[width-1]^b[width-1]) && ~\|mul_prod_r[width-2:0])) \|\|`
	`\|mul_prod_r[2*width-1:32];`

`ov_we = 1;`	`ov_we = 1;`
`end`	`end`
`OR1200_ALUOP_MULU : begin	`OR1200_ALUOP_MULU : begin
`// Overflow on unsigned multiply is simpler.`	`// Overflow on unsigned multiply is simpler.`
`ovforw = mul_prod_r[32];`	`ovforw = \|mul_prod_r[2*width-1:32];`
`ov_we = 1;`	`ov_we = 1;`
`end`	`end`
`endif // `ifdef OR1200_MULT_IMPLEMENTED	`endif // `ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_DIV_IMPLEMENTED	`ifdef OR1200_DIV_IMPLEMENTED
`OR1200_ALUOP_DIVU,	`OR1200_ALUOP_DIVU,
`OR1200_ALUOP_DIV: begin	`OR1200_ALUOP_DIV: begin
`// Overflow on divide by zero`	`// Overflow on divide by zero or -2^(width-1)/-1`
`ovforw = div_by_zero;`	`ovforw = div_by_zero \|\| (a==32'h8000_0000 && b==32'hffff_ffff);`
`ov_we = 1;`	`ov_we = 1;`
`end`	`end`
`endif	`endif
`endif // `ifdef OR1200_IMPL_OV	`endif // `ifdef OR1200_IMPL_OV
`default: begin`	`default: begin`