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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's Top level multiplier, divider and MAC ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// Description ////
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//// Multiplier is 32x32 however multiply instructions only ////
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//// use lower 32 bits of the result. MAC is 32x32=64+64. ////
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//// ////
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//// To Do: ////
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//// - make signed division better, w/o negating the operands ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: or1200_mult_mac.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Bugs fixed.
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_mult_mac(
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// Clock and reset
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clk, rst,
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// Multiplier/MAC interface
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ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r,
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// SPR interface
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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);
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parameter width = `OR1200_OPERAND_WIDTH;
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//
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// I/O
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//
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//
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// Clock and reset
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//
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input clk;
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input rst;
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//
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// Multiplier/MAC interface
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//
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input ex_freeze;
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input id_macrc_op;
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input macrc_op;
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input [width-1:0] a;
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input [width-1:0] b;
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input [`OR1200_MACOP_WIDTH-1:0] mac_op;
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input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
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output [width-1:0] result;
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output mac_stall_r;
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//
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// SPR interface
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//
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input spr_cs;
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input spr_write;
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input [31:0] spr_addr;
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input [31:0] spr_dat_i;
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output [31:0] spr_dat_o;
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//
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// Internal wires and regs
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//
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`ifdef OR1200_MULT_IMPLEMENTED
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reg [width-1:0] result;
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reg [2*width-1:0] mul_prod_r;
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`else
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wire [width-1:0] result;
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wire [2*width-1:0] mul_prod_r;
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`endif
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wire [2*width-1:0] mul_prod;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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`ifdef OR1200_MAC_IMPLEMENTED
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
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reg mac_stall_r;
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reg [63:0] mac_r;
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`else
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
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wire mac_stall_r;
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wire [63:0] mac_r;
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`endif
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wire [width-1:0] x;
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wire [width-1:0] y;
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wire spr_maclo_we;
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wire spr_machi_we;
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wire alu_op_div_divu;
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wire alu_op_div;
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reg div_free;
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`ifdef OR1200_DIV_IMPLEMENTED
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wire [width-1:0] div_tmp;
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reg [5:0] div_cntr;
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`endif
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//
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// Combinatorial logic
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//
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`ifdef OR1200_MAC_IMPLEMENTED
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assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
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assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
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assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
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`else
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assign spr_maclo_we = 1'b0;
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assign spr_machi_we = 1'b0;
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assign spr_dat_o = 32'h0000_0000;
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`endif
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`ifdef OR1200_LOWPWR_MULT
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assign x = (alu_op_div & a[31]) ? ~a + 1'b1 :
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alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ?
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a : 32'h0000_0000;
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assign y = (alu_op_div & b[31]) ? ~b + 1'b1 :
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alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ?
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b : 32'h0000_0000;
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`else
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assign x = alu_op_div & a[31] ? ~a + 32'b1 : a;
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assign y = alu_op_div & b[31] ? ~b + 32'b1 : b;
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`endif
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`ifdef OR1200_DIV_IMPLEMENTED
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assign alu_op_div = (alu_op == `OR1200_ALUOP_DIV);
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assign alu_op_div_divu = alu_op_div | (alu_op == `OR1200_ALUOP_DIVU);
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assign div_tmp = mul_prod_r[63:32] - y;
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`else
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assign alu_op_div = 1'b0;
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assign alu_op_div_divu = 1'b0;
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`endif
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`ifdef OR1200_MULT_IMPLEMENTED
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//
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// Select result of current ALU operation to be forwarded
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// to next instruction and to WB stage
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//
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always @*
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casex(alu_op) // synopsys parallel_case
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`ifdef OR1200_DIV_IMPLEMENTED
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`OR1200_ALUOP_DIV: begin
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result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];
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end
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`OR1200_ALUOP_DIVU,
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`endif
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`OR1200_ALUOP_MUL: begin
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result = mul_prod_r[31:0];
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end
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default:
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`ifdef OR1200_MAC_SHIFTBY
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result = mac_r[`OR1200_MAC_SHIFTBY+31:`OR1200_MAC_SHIFTBY];
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`else
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result = mac_r[31:0];
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`endif
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endcase
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//
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// Instantiation of the multiplier
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//
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`ifdef OR1200_ASIC_MULTP2_32X32
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or1200_amultp2_32x32 or1200_amultp2_32x32(
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.X(x),
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.Y(y),
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.RST(rst),
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.CLK(clk),
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.P(mul_prod)
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);
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`else // OR1200_ASIC_MULTP2_32X32
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or1200_gmultp2_32x32 or1200_gmultp2_32x32(
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.X(x),
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.Y(y),
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.RST(rst),
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.CLK(clk),
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.P(mul_prod)
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);
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`endif // OR1200_ASIC_MULTP2_32X32
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//
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// Registered output from the multiplier and
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// an optional divider
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//
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always @(`OR1200_RST_EVENT rst or posedge clk)
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if (rst == `OR1200_RST_VALUE) begin
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mul_prod_r <= 64'h0000_0000_0000_0000;
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div_free <= 1'b1;
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`ifdef OR1200_DIV_IMPLEMENTED
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div_cntr <= 6'b00_0000;
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`endif
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end
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`ifdef OR1200_DIV_IMPLEMENTED
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else if (|div_cntr) begin
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if (div_tmp[31])
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mul_prod_r <= {mul_prod_r[62:0], 1'b0};
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else
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mul_prod_r <= {div_tmp[30:0], mul_prod_r[31:0], 1'b1};
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div_cntr <= div_cntr - 1'b1;
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end
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else if (alu_op_div_divu && div_free) begin
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mul_prod_r <= {31'b0, x[31:0], 1'b0};
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div_cntr <= 6'b10_0000;
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div_free <= 1'b0;
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end
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`endif // OR1200_DIV_IMPLEMENTED
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else if (div_free | !ex_freeze) begin
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mul_prod_r <= mul_prod[63:0];
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div_free <= 1'b1;
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end
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`else // OR1200_MULT_IMPLEMENTED
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assign result = {width{1'b0}};
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assign mul_prod = {2*width{1'b0}};
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assign mul_prod_r = {2*width{1'b0}};
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`endif // OR1200_MULT_IMPLEMENTED
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`ifdef OR1200_MAC_IMPLEMENTED
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// Signal to indicate when we should check for new MAC op
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reg ex_freeze_r;
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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ex_freeze_r <= 1'b1;
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else
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ex_freeze_r <= ex_freeze;
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//
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// Propagation of l.mac opcode, only register it for one cycle
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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mac_op_r1 <= `OR1200_MACOP_WIDTH'b0;
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else
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mac_op_r1 <= !ex_freeze_r ? mac_op : `OR1200_MACOP_WIDTH'b0;
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//
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// Propagation of l.mac opcode
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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mac_op_r2 <= `OR1200_MACOP_WIDTH'b0;
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else
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mac_op_r2 <= mac_op_r1;
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//
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// Propagation of l.mac opcode
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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mac_op_r3 <= `OR1200_MACOP_WIDTH'b0;
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else
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mac_op_r3 <= mac_op_r2;
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//
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// Implementation of MAC
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//
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always @(`OR1200_RST_EVENT rst or posedge clk)
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if (rst == `OR1200_RST_VALUE)
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mac_r <= 64'h0000_0000_0000_0000;
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`ifdef OR1200_MAC_SPR_WE
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else if (spr_maclo_we)
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mac_r[31:0] <= spr_dat_i;
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else if (spr_machi_we)
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mac_r[63:32] <= spr_dat_i;
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`endif
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else if (mac_op_r3 == `OR1200_MACOP_MAC)
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mac_r <= mac_r + mul_prod_r;
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else if (mac_op_r3 == `OR1200_MACOP_MSB)
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mac_r <= mac_r - mul_prod_r;
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else if (macrc_op && !ex_freeze)
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mac_r <= 64'h0000_0000_0000_0000;
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//
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// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
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// in EX stage (e.g. inside multiplier)
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// This stall signal is also used by the divider.
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//
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always @(`OR1200_RST_EVENT rst or posedge clk)
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if (rst == `OR1200_RST_VALUE)
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mac_stall_r <= 1'b0;
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else
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mac_stall_r <= (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & (id_macrc_op | mac_stall_r)
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`ifdef OR1200_DIV_IMPLEMENTED
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| (|div_cntr)
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`endif
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;
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`else // OR1200_MAC_IMPLEMENTED
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assign mac_stall_r = 1'b0;
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assign mac_r = {2*width{1'b0}};
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assign mac_op_r1 = `OR1200_MACOP_WIDTH'b0;
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assign mac_op_r2 = `OR1200_MACOP_WIDTH'b0;
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assign mac_op_r3 = `OR1200_MACOP_WIDTH'b0;
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`endif // OR1200_MAC_IMPLEMENTED
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endmodule
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