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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's Embedded Memory ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// Description ////
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//// Embedded Memory . ////
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//// ////
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//// To Do: ////
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//// - QMEM and IC/DC muxes can be removed except for cycstb ////
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//// (now are is there for easier debugging) ////
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//// - currently arbitration is slow and stores take 2 clocks ////
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//// (final debugged version will be faster) ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2003 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: or1200_qmem_top.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Coding style changed.
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//
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// Revision 1.3 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.2 2004/04/05 08:40:26 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.1.2.4 2004/01/11 22:45:46 andreje
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// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
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//
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// Revision 1.1.2.3 2003/12/17 13:36:58 simons
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// Qmem mbist signals fixed.
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//
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// Revision 1.1.2.2 2003/12/09 11:46:48 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.1.2.1 2003/07/08 15:45:26 lampret
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// Added embedded memory QMEM.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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`define OR1200_QMEMFSM_IDLE 3'd0
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`define OR1200_QMEMFSM_STORE 3'd1
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`define OR1200_QMEMFSM_LOAD 3'd2
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`define OR1200_QMEMFSM_FETCH 3'd3
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//
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// Embedded memory
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//
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module or1200_qmem_top(
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// Rst, clk and clock control
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clk, rst,
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`ifdef OR1200_BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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// QMEM and CPU/IMMU
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qmemimmu_adr_i,
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qmemimmu_cycstb_i,
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qmemimmu_ci_i,
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qmemicpu_sel_i,
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qmemicpu_tag_i,
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qmemicpu_dat_o,
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qmemicpu_ack_o,
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qmemimmu_rty_o,
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qmemimmu_err_o,
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qmemimmu_tag_o,
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// QMEM and IC
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icqmem_adr_o,
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icqmem_cycstb_o,
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icqmem_ci_o,
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icqmem_sel_o,
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icqmem_tag_o,
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icqmem_dat_i,
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icqmem_ack_i,
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icqmem_rty_i,
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icqmem_err_i,
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icqmem_tag_i,
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// QMEM and CPU/DMMU
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qmemdmmu_adr_i,
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qmemdmmu_cycstb_i,
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qmemdmmu_ci_i,
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qmemdcpu_we_i,
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qmemdcpu_sel_i,
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qmemdcpu_tag_i,
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qmemdcpu_dat_i,
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qmemdcpu_dat_o,
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qmemdcpu_ack_o,
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qmemdcpu_rty_o,
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qmemdmmu_err_o,
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qmemdmmu_tag_o,
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// QMEM and DC
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dcqmem_adr_o,
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dcqmem_cycstb_o,
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dcqmem_ci_o,
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dcqmem_we_o,
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dcqmem_sel_o,
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dcqmem_tag_o,
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dcqmem_dat_o,
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dcqmem_dat_i,
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dcqmem_ack_i,
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dcqmem_rty_i,
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dcqmem_err_i,
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dcqmem_tag_i
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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//
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// I/O
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//
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//
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// Clock and reset
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//
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input clk;
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input rst;
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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`endif
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//
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// QMEM and CPU/IMMU
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//
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input [31:0] qmemimmu_adr_i;
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input qmemimmu_cycstb_i;
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input qmemimmu_ci_i;
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input [3:0] qmemicpu_sel_i;
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input [3:0] qmemicpu_tag_i;
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output [31:0] qmemicpu_dat_o;
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output qmemicpu_ack_o;
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output qmemimmu_rty_o;
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output qmemimmu_err_o;
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output [3:0] qmemimmu_tag_o;
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//
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// QMEM and IC
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//
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output [31:0] icqmem_adr_o;
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output icqmem_cycstb_o;
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output icqmem_ci_o;
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output [3:0] icqmem_sel_o;
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output [3:0] icqmem_tag_o;
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input [31:0] icqmem_dat_i;
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input icqmem_ack_i;
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input icqmem_rty_i;
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input icqmem_err_i;
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input [3:0] icqmem_tag_i;
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//
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// QMEM and CPU/DMMU
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//
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input [31:0] qmemdmmu_adr_i;
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input qmemdmmu_cycstb_i;
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input qmemdmmu_ci_i;
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input qmemdcpu_we_i;
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input [3:0] qmemdcpu_sel_i;
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input [3:0] qmemdcpu_tag_i;
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input [31:0] qmemdcpu_dat_i;
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output [31:0] qmemdcpu_dat_o;
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output qmemdcpu_ack_o;
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output qmemdcpu_rty_o;
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output qmemdmmu_err_o;
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output [3:0] qmemdmmu_tag_o;
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//
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// QMEM and DC
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//
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output [31:0] dcqmem_adr_o;
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output dcqmem_cycstb_o;
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output dcqmem_ci_o;
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output dcqmem_we_o;
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output [3:0] dcqmem_sel_o;
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output [3:0] dcqmem_tag_o;
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output [dw-1:0] dcqmem_dat_o;
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input [dw-1:0] dcqmem_dat_i;
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input dcqmem_ack_i;
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input dcqmem_rty_i;
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input dcqmem_err_i;
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input [3:0] dcqmem_tag_i;
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`ifdef OR1200_QMEM_IMPLEMENTED
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//
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// Internal regs and wires
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//
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wire iaddr_qmem_hit;
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wire daddr_qmem_hit;
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reg [2:0] state;
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reg qmem_dack;
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reg qmem_iack;
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wire [31:0] qmem_di;
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wire [31:0] qmem_do;
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wire qmem_en;
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wire qmem_we;
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`ifdef OR1200_QMEM_BSEL
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wire [3:0] qmem_sel;
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`endif
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wire [31:0] qmem_addr;
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`ifdef OR1200_QMEM_ACK
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wire qmem_ack;
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`else
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wire qmem_ack = 1'b1;
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`endif
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//
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// QMEM and CPU/IMMU
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//
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assign qmemicpu_dat_o = qmem_iack ? qmem_do : icqmem_dat_i;
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assign qmemicpu_ack_o = qmem_iack ? 1'b1 : icqmem_ack_i;
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assign qmemimmu_rty_o = qmem_iack ? 1'b0 : icqmem_rty_i;
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assign qmemimmu_err_o = qmem_iack ? 1'b0 : icqmem_err_i;
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assign qmemimmu_tag_o = qmem_iack ? 4'h0 : icqmem_tag_i;
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//
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// QMEM and IC
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//
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assign icqmem_adr_o = iaddr_qmem_hit ? 32'h0000_0000 : qmemimmu_adr_i;
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assign icqmem_cycstb_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_cycstb_i;
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assign icqmem_ci_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_ci_i;
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assign icqmem_sel_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_sel_i;
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assign icqmem_tag_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_tag_i;
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//
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// QMEM and CPU/DMMU
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//
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assign qmemdcpu_dat_o = daddr_qmem_hit ? qmem_do : dcqmem_dat_i;
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assign qmemdcpu_ack_o = daddr_qmem_hit ? qmem_dack : dcqmem_ack_i;
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assign qmemdcpu_rty_o = daddr_qmem_hit ? ~qmem_dack : dcqmem_rty_i;
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assign qmemdmmu_err_o = daddr_qmem_hit ? 1'b0 : dcqmem_err_i;
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assign qmemdmmu_tag_o = daddr_qmem_hit ? 4'h0 : dcqmem_tag_i;
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//
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// QMEM and DC
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//
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assign dcqmem_adr_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdmmu_adr_i;
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assign dcqmem_cycstb_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_cycstb_i;
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assign dcqmem_ci_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_ci_i;
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assign dcqmem_we_o = daddr_qmem_hit ? 1'b0 : qmemdcpu_we_i;
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assign dcqmem_sel_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_sel_i;
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assign dcqmem_tag_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_tag_i;
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assign dcqmem_dat_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdcpu_dat_i;
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//
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// Address comparison whether QMEM was hit
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//
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`ifdef OR1200_QMEM_IADDR
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assign iaddr_qmem_hit = (qmemimmu_adr_i & `OR1200_QMEM_IMASK) == `OR1200_QMEM_IADDR;
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`else
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assign iaddr_qmem_hit = 1'b0;
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`endif
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`ifdef OR1200_QMEM_DADDR
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assign daddr_qmem_hit = (qmemdmmu_adr_i & `OR1200_QMEM_DMASK) == `OR1200_QMEM_DADDR;
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`else
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assign daddr_qmem_hit = 1'b0;
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`endif
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//
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//
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//
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assign qmem_en = iaddr_qmem_hit & qmemimmu_cycstb_i | daddr_qmem_hit & qmemdmmu_cycstb_i;
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assign qmem_we = qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i;
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`ifdef OR1200_QMEM_BSEL
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assign qmem_sel = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdcpu_sel_i : qmemicpu_sel_i;
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`endif
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assign qmem_di = qmemdcpu_dat_i;
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assign qmem_addr = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdmmu_adr_i : qmemimmu_adr_i;
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//
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// QMEM control FSM
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//
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always @(`OR1200_RST_EVENT rst or posedge clk)
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if (rst == `OR1200_RST_VALUE) begin
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state <= `OR1200_QMEMFSM_IDLE;
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qmem_dack <= 1'b0;
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qmem_iack <= 1'b0;
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end
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else case (state) // synopsys parallel_case
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`OR1200_QMEMFSM_IDLE: begin
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if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
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state <= `OR1200_QMEMFSM_STORE;
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qmem_dack <= 1'b1;
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qmem_iack <= 1'b0;
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end
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else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
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state <= `OR1200_QMEMFSM_LOAD;
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qmem_dack <= 1'b1;
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qmem_iack <= 1'b0;
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end
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else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
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state <= `OR1200_QMEMFSM_FETCH;
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qmem_iack <= 1'b1;
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qmem_dack <= 1'b0;
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end
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end
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`OR1200_QMEMFSM_STORE: begin
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if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
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state <= `OR1200_QMEMFSM_STORE;
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qmem_dack <= 1'b1;
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qmem_iack <= 1'b0;
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end
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else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
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state <= `OR1200_QMEMFSM_LOAD;
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qmem_dack <= 1'b1;
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qmem_iack <= 1'b0;
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end
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else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
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state <= `OR1200_QMEMFSM_FETCH;
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qmem_iack <= 1'b1;
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qmem_dack <= 1'b0;
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end
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else begin
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state <= `OR1200_QMEMFSM_IDLE;
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qmem_dack <= 1'b0;
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qmem_iack <= 1'b0;
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end
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end
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`OR1200_QMEMFSM_LOAD: begin
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if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
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state <= `OR1200_QMEMFSM_STORE;
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qmem_dack <= 1'b1;
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qmem_iack <= 1'b0;
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end
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else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
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state <= `OR1200_QMEMFSM_LOAD;
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qmem_dack <= 1'b1;
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qmem_iack <= 1'b0;
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end
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else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
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state <= `OR1200_QMEMFSM_FETCH;
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qmem_iack <= 1'b1;
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qmem_dack <= 1'b0;
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end
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else begin
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state <= `OR1200_QMEMFSM_IDLE;
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qmem_dack <= 1'b0;
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qmem_iack <= 1'b0;
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end
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end
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`OR1200_QMEMFSM_FETCH: begin
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if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
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state <= `OR1200_QMEMFSM_STORE;
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qmem_dack <= 1'b1;
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qmem_iack <= 1'b0;
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end
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else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
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state <= `OR1200_QMEMFSM_LOAD;
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qmem_dack <= 1'b1;
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qmem_iack <= 1'b0;
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end
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else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
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state <= `OR1200_QMEMFSM_FETCH;
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qmem_iack <= 1'b1;
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qmem_dack <= 1'b0;
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end
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else begin
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state <= `OR1200_QMEMFSM_IDLE;
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qmem_dack <= 1'b0;
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qmem_iack <= 1'b0;
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end
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end
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default: begin
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state <= `OR1200_QMEMFSM_IDLE;
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qmem_dack <= 1'b0;
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qmem_iack <= 1'b0;
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end
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endcase
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|
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//
|
|
// Instantiation of embedded memory
|
|
//
|
|
or1200_spram_2048x32 or1200_qmem_ram(
|
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.clk(clk),
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.rst(rst),
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|
`ifdef OR1200_BIST
|
|
// RAM BIST
|
|
.mbist_si_i(mbist_si_i),
|
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.mbist_so_o(mbist_so_o),
|
|
.mbist_ctrl_i(mbist_ctrl_i),
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`endif
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|
.addr(qmem_addr[12:2]),
|
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`ifdef OR1200_QMEM_BSEL
|
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.sel(qmem_sel),
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`endif
|
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`ifdef OR1200_QMEM_ACK
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.ack(qmem_ack),
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`endif
|
|
.ce(qmem_en),
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.we(qmem_we),
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.oe(1'b1),
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.di(qmem_di),
|
|
.doq(qmem_do)
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|
);
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|
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`else // OR1200_QMEM_IMPLEMENTED
|
|
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|
//
|
|
// QMEM and CPU/IMMU
|
|
//
|
|
assign qmemicpu_dat_o = icqmem_dat_i;
|
|
assign qmemicpu_ack_o = icqmem_ack_i;
|
|
assign qmemimmu_rty_o = icqmem_rty_i;
|
|
assign qmemimmu_err_o = icqmem_err_i;
|
|
assign qmemimmu_tag_o = icqmem_tag_i;
|
|
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//
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// QMEM and IC
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//
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assign icqmem_adr_o = qmemimmu_adr_i;
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assign icqmem_cycstb_o = qmemimmu_cycstb_i;
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assign icqmem_ci_o = qmemimmu_ci_i;
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assign icqmem_sel_o = qmemicpu_sel_i;
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assign icqmem_tag_o = qmemicpu_tag_i;
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//
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// QMEM and CPU/DMMU
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//
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assign qmemdcpu_dat_o = dcqmem_dat_i;
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assign qmemdcpu_ack_o = dcqmem_ack_i;
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assign qmemdcpu_rty_o = dcqmem_rty_i;
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assign qmemdmmu_err_o = dcqmem_err_i;
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assign qmemdmmu_tag_o = dcqmem_tag_i;
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//
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// QMEM and DC
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//
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assign dcqmem_adr_o = qmemdmmu_adr_i;
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assign dcqmem_cycstb_o = qmemdmmu_cycstb_i;
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assign dcqmem_ci_o = qmemdmmu_ci_i;
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assign dcqmem_we_o = qmemdcpu_we_i;
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assign dcqmem_sel_o = qmemdcpu_sel_i;
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assign dcqmem_tag_o = qmemdcpu_tag_i;
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assign dcqmem_dat_o = qmemdcpu_dat_i;
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`ifdef OR1200_BIST
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assign mbist_so_o = mbist_si_i;
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`endif
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`endif
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endmodule
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No newline at end of file
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No newline at end of file
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