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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's reg2mem aligner ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// Description ////
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//// Aligns register data to memory alignment. ////
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//// ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: or1200_reg2mem.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// No update
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//
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// Revision 1.2 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.8 2001/10/19 23:28:46 lampret
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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//
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// Revision 1.7 2001/10/14 13:12:10 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.1 2001/07/20 00:46:21 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_reg2mem(addr, lsu_op, regdata, memdata);
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parameter width = `OR1200_OPERAND_WIDTH;
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//
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// I/O
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//
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input [1:0] addr;
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input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
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input [width-1:0] regdata;
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output [width-1:0] memdata;
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//
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// Internal regs and wires
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//
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reg [7:0] memdata_hh;
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reg [7:0] memdata_hl;
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reg [7:0] memdata_lh;
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reg [7:0] memdata_ll;
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assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll};
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//
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// Mux to memdata[31:24]
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//
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always @(lsu_op or addr or regdata) begin
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casex({lsu_op, addr[1:0]}) // synopsys parallel_case
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{`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
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{`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
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default : memdata_hh = regdata[31:24];
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endcase
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end
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//
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// Mux to memdata[23:16]
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//
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always @(lsu_op or addr or regdata) begin
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casex({lsu_op, addr[1:0]}) // synopsys parallel_case
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{`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
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default : memdata_hl = regdata[7:0];
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endcase
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end
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//
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// Mux to memdata[15:8]
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//
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always @(lsu_op or addr or regdata) begin
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casex({lsu_op, addr[1:0]}) // synopsys parallel_case
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{`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
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default : memdata_lh = regdata[15:8];
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endcase
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end
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//
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// Mux to memdata[7:0]
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//
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always @(regdata)
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memdata_ll = regdata[7:0];
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endmodule
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