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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_rf.v] - Diff between revs 482 and 483

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Rev 482 Rev 483
Line 54... Line 54... 
 
 
 
 
module or1200_rf(
 
module or1200_rf(
 
        // Clock and reset
 
        // Clock and reset
 
        clk, rst,
 
        clk, rst,
 
 
 
 
 
 
 
`ifdef OR1200_RAM_PARITY
 
 
 
        // Parity error indicator
 
 
 
        p_err,
 
 
 
`endif
 
 
 
 
 
        // Write i/f
 
        // Write i/f
 
        cy_we_i, cy_we_o, supv, wb_freeze, addrw, dataw, we, flushpipe,
 
        cy_we_i, cy_we_o, supv, wb_freeze, addrw, dataw, we, flushpipe,
 
 
 
 
 
        // Read i/f
 
        // Read i/f
 
        id_freeze, addra, addrb, dataa, datab, rda, rdb,
 
        id_freeze, addra, addrb, dataa, datab, rda, rdb,
Line 110... Line 115... 
input   [31:0]                   spr_addr;
 
input   [31:0]                   spr_addr;
 
input   [31:0]                   spr_dat_i;
 
input   [31:0]                   spr_dat_i;
 
output  [31:0]                   spr_dat_o;
 
output  [31:0]                   spr_dat_o;
 
input                           du_read;
 
input                           du_read;
 
 
 
 
 
 
 
`ifdef OR1200_RAM_PARITY
 
 
 
output                          p_err;
 
 
 
wire [1:0]                       p_err_wire;
 
 
 
reg                             ena_r, enb_r;
 
 
 
 
 
 
 
`endif
 
 
 
 
 
 
 
 
 
//
 
//
 
// Internal wires and regs
 
// Internal wires and regs
 
//
 
//
 
wire    [dw-1:0]         from_rfa;
 
wire    [dw-1:0]         from_rfa;
 
wire    [dw-1:0]         from_rfb;
 
wire    [dw-1:0]         from_rfb;
Line 148... Line 161... 
   always @(posedge clk)
 
   always @(posedge clk)
 
     spr_du_cs <= spr_cs & du_read;
 
     spr_du_cs <= spr_cs & du_read;
 
 
 
 
 
   assign spr_cs_fe = spr_du_cs & !(spr_cs & du_read);
 
   assign spr_cs_fe = spr_du_cs & !(spr_cs & du_read);
 
 
 
 
 
 
 
 
 
//
 
//
 
// SPR access is valid when spr_cs is asserted and
 
// SPR access is valid when spr_cs is asserted and
 
// SPR address matches GPR addresses
 
// SPR address matches GPR addresses
 
//
 
//
 
assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
 
assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
Line 179... Line 191... 
                  spr_cs_fe ? addra_last : addra;
 
                  spr_cs_fe ? addra_last : addra;
 
 
 
 
 
//
 
//
 
// RF write address is either from SPRS or normal from CPU control
 
// RF write address is either from SPRS or normal from CPU control
 
//
 
//
 
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
 
assign rf_addrw = rst ? 0 : (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
 
 
 
 
 
//
 
//
 
// RF write data is either from SPRS or normal from CPU datapath
 
// RF write data is either from SPRS or normal from CPU datapath
 
//
 
//
 
assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;
 
assign rf_dataw = rst ? 0 : (spr_valid & spr_write) ? spr_dat_i : dataw;
 
 
 
 
 
//
 
//
 
// RF write enable is either from SPRS or normal from CPU control
 
// RF write enable is either from SPRS or normal from CPU control
 
//
 
//
 
always @(`OR1200_RST_EVENT rst or posedge clk)
 
always @(`OR1200_RST_EVENT rst or posedge clk)
 
        if (rst == `OR1200_RST_VALUE)
 
        if (rst == `OR1200_RST_VALUE)
 
                rf_we_allow <=  1'b1;
 
                rf_we_allow <=  1'b1;
 
        else if (~wb_freeze)
 
        else if (~wb_freeze)
 
                rf_we_allow <=  ~flushpipe;
 
                rf_we_allow <=  ~flushpipe;
 
 
 
 
 
//assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
 
assign rf_we = rst ? 1 : ((spr_valid & spr_write) | (we & ~wb_freeze)) &
 
assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;
 
               rf_we_allow;
 
//assign cy_we_o = cy_we_i && rf_we;
 
 
 
assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
 
 
 
 
 
 
 
 
 
assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
 
 
 
 
 
//
 
//
 
// CS RF A asserted when instruction reads operand A and ID stage
 
// CS RF A asserted when instruction reads operand A and ID stage
 
// is not stalled
 
// is not stalled
 
//
 
//
 
//assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils
 
assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe;
 
assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe;      // probably works with fixed binutils
 
 
 
// assign rf_ena = 1'b1;                        // does not work with single-stepping
 
 
 
//assign rf_ena = ~id_freeze | spr_valid;       // works with broken binutils 
 
 
 
 
 
 
//
 
//
 
// CS RF B asserted when instruction reads operand B and ID stage
 
// CS RF B asserted when instruction reads operand B and ID stage
 
// is not stalled
 
// is not stalled
 
//
 
//
 
//assign rf_enb = rdb & ~id_freeze | spr_valid;
 
 
 
assign rf_enb = rdb & ~id_freeze;
 
assign rf_enb = rdb & ~id_freeze;
 
// assign rf_enb = 1'b1;
 
 
 
//assign rf_enb = ~id_freeze | spr_valid;       // works with broken binutils 
`ifdef OR1200_RAM_PARITY
 
 
 
   always @(posedge clk)
 
 
 
     if (rst) begin
 
 
 
        ena_r <= 0;
 
 
 
        enb_r <= 0;
 
 
 
     end
 
 
 
     else if (p_err) begin
 
 
 
        ena_r <= 0;
 
 
 
        enb_r <= 0;
 
 
 
     end
 
 
 
     else begin
 
 
 
        ena_r <= rf_ena;
 
 
 
        enb_r <= rf_enb;
 
 
 
     end
 
 
 
 
 
 
 
 
 
 
 
   assign p_err = (p_err_wire[0] & ena_r) | (p_err_wire[1] & enb_r);
 
 
 
 
 
 
 
`endif
 
 
 
 
 
`ifdef OR1200_RFRAM_TWOPORT
 
`ifdef OR1200_RFRAM_TWOPORT
 
 
 
 
 
//
 
//
 
// Instantiation of register file two-port RAM A
 
// Instantiation of register file two-port RAM A
Line 271... Line 296... 
        .addr_b(rf_addrw),
 
        .addr_b(rf_addrw),
 
        .di_b(rf_dataw),
 
        .di_b(rf_dataw),
 
        .do_b()
 
        .do_b()
 
);
 
);
 
 
 
 
 
 
 
 `ifdef OR1200_RAM_PARITY
 
 
 
   assign p_err_wire = 0;
 
 
 
 `endif
 
 
 
 
 
 
 
 
 
`else
 
`else
 
 
 
 
 
`ifdef OR1200_RFRAM_DUALPORT
 
`ifdef OR1200_RFRAM_DUALPORT
 
 
 
 
 
//
 
//
Line 285... Line 315... 
      .aw(5),
 
      .aw(5),
 
      .dw(32)
 
      .dw(32)
 
      )
 
      )
 
   rf_a
 
   rf_a
 
     (
 
     (
 
 
 
      .rst(rst),
 
      // Port A
 
      // Port A
 
      .clk_a(clk),
 
      .clk_a(clk),
 
      .ce_a(rf_ena),
 
      .ce_a(rf_ena),
 
      .addr_a(rf_addra),
 
      .addr_a(rf_addra),
 
      .do_a(from_rfa),
 
      .do_a(from_rfa),
Line 299... Line 330... 
      .we_b(rf_we),
 
      .we_b(rf_we),
 
      .addr_b(rf_addrw),
 
      .addr_b(rf_addrw),
 
      .di_b(rf_dataw)
 
      .di_b(rf_dataw)
 
 
 
 
 
`ifdef OR1200_RAM_PARITY
 
`ifdef OR1200_RAM_PARITY
 
      , .p_err()
 
      , .p_err(p_err_wire[0])
 
`endif
 
`endif
 
      );
 
      );
 
 
 
 
 
   //
 
   //
 
   // Instantiation of register file two-port RAM B
 
   // Instantiation of register file two-port RAM B
Line 313... Line 344... 
      .aw(5),
 
      .aw(5),
 
      .dw(32)
 
      .dw(32)
 
      )
 
      )
 
   rf_b
 
   rf_b
 
     (
 
     (
 
 
 
      .rst(rst),
 
      // Port A
 
      // Port A
 
      .clk_a(clk),
 
      .clk_a(clk),
 
      .ce_a(rf_enb),
 
      .ce_a(rf_enb),
 
      .addr_a(addrb),
 
      .addr_a(addrb),
 
      .do_a(from_rfb),
 
      .do_a(from_rfb),
Line 325... Line 357... 
      .clk_b(clk),
 
      .clk_b(clk),
 
      .ce_b(rf_we),
 
      .ce_b(rf_we),
 
      .we_b(rf_we),
 
      .we_b(rf_we),
 
      .addr_b(rf_addrw),
 
      .addr_b(rf_addrw),
 
      .di_b(rf_dataw)
 
      .di_b(rf_dataw)
 
 
 
 
 
`ifdef OR1200_RAM_PARITY
 
`ifdef OR1200_RAM_PARITY
 
      , .p_err()
 
      , .p_err(p_err_wire[1])
 
`endif
 
`endif
 
 
 
 
 
      );
 
      );
 
 
 
 
 
`else
 
`else
Line 360... Line 393... 
        .we_w(rf_we),
 
        .we_w(rf_we),
 
        .addr_w(rf_addrw),
 
        .addr_w(rf_addrw),
 
        .di_w(rf_dataw)
 
        .di_w(rf_dataw)
 
);
 
);
 
 
 
 
 
 
 
 `ifdef OR1200_RAM_PARITY
 
 
 
   assign p_err_wire = 0;
 
 
 
 `endif
 
 
 
 
 
`else
 
`else
 
 
 
 
 
//
 
//
 
// RFRAM type not specified
 
// RFRAM type not specified
 
//
 
//

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