URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_rfram_generic.v] - Diff between revs 462 and 478

Rev 462	Rev 478
Line 124...	Line 124...
`reg [32*dw-1:0] mem;`	`reg [32*dw-1:0] mem;`
`endif	`endif
`reg [dw-1:0] do_a;`	`reg [dw-1:0] do_a;`
`reg [dw-1:0] do_b;`	`reg [dw-1:0] do_b;`

	`ifdef verilator
`// Function to access GPRs (for use by Verilator). No need to hide this one`	`// Function to access GPRs (for use by Verilator). No need to hide this one`
`// from the simulator, since it has an input (as required by IEEE 1364-2001).`	`// from the simulator, since it has an input (as required by IEEE 1364-2001).`
`function [31:0] get_gpr;`	`function [31:0] get_gpr;`
`// verilator public`	`// verilator public`
`input [aw-1:0] gpr_no;`	`input [aw-1:0] gpr_no;`
Line 189...	Line 190...
`mem[gpr_no*32 + 3] = value[ 3];`	`mem[gpr_no*32 + 3] = value[ 3];`
`mem[gpr_no*32 + 2] = value[ 2];`	`mem[gpr_no*32 + 2] = value[ 2];`
`mem[gpr_no*32 + 1] = value[ 1];`	`mem[gpr_no*32 + 1] = value[ 1];`
`mem[gpr_no*32 + 0] = value[ 0];`	`mem[gpr_no*32 + 0] = value[ 0];`

	`set_gpr = 0;`

`endfunction // set_gpr`	`endfunction // set_gpr`
	`endif // `ifdef verilator

`//`	`//`
`// Write port`	`// Write port`
`//`	`//`
always @(posedge clk or `OR1200_RST_EVENT rst)	always @(posedge clk or `OR1200_RST_EVENT rst)