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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's Store Buffer FIFO ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// Description ////
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//// Implementation of store buffer FIFO. ////
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//// ////
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//// To Do: ////
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//// - N/A ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: or1200_sb_fifo.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// No update
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//
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// Revision 1.3 2002/11/06 13:53:41 simons
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// SB mem width fixed.
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//
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// Revision 1.2 2002/08/22 02:18:55 lampret
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// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
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//
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// Revision 1.1 2002/08/18 19:53:08 lampret
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// Added store buffer.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_sb_fifo(
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clk_i, rst_i, dat_i, wr_i, rd_i, dat_o, full_o, empty_o
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);
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parameter dw = 68;
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parameter fw = `OR1200_SB_LOG;
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parameter fl = `OR1200_SB_ENTRIES;
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//
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// FIFO signals
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//
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input clk_i; // Clock
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input rst_i; // Reset
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input [dw-1:0] dat_i; // Input data bus
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input wr_i; // Write request
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input rd_i; // Read request
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output [dw-1:0] dat_o; // Output data bus
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output full_o; // FIFO full
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output empty_o;// FIFO empty
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//
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// Internal regs
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//
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reg [dw-1:0] mem [fl-1:0];
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reg [dw-1:0] dat_o;
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reg [fw+1:0] cntr;
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reg [fw-1:0] wr_pntr;
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reg [fw-1:0] rd_pntr;
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reg empty_o;
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reg full_o;
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always @(posedge clk_i or `OR1200_RST_EVENT rst_i)
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if (rst_i == `OR1200_RST_VALUE) begin
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full_o <= 1'b0;
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empty_o <= 1'b1;
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wr_pntr <= {fw{1'b0}};
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rd_pntr <= {fw{1'b0}};
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cntr <= {fw+2{1'b0}};
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dat_o <= {dw{1'b0}};
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end
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else if (wr_i && rd_i) begin // FIFO Read and Write
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mem[wr_pntr] <= dat_i;
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if (wr_pntr >= fl-1)
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wr_pntr <= {fw{1'b0}};
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else
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wr_pntr <= wr_pntr + 1'b1;
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if (empty_o) begin
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dat_o <= dat_i;
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end
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else begin
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dat_o <= mem[rd_pntr];
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end
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if (rd_pntr >= fl-1)
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rd_pntr <= {fw{1'b0}};
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else
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rd_pntr <= rd_pntr + 1'b1;
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end
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else if (wr_i && !full_o) begin // FIFO Write
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mem[wr_pntr] <= dat_i;
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cntr <= cntr + 1'b1;
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empty_o <= 1'b0;
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if (cntr >= (fl-1)) begin
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full_o <= 1'b1;
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cntr <= fl;
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end
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if (wr_pntr >= fl-1)
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wr_pntr <= {fw{1'b0}};
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else
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wr_pntr <= wr_pntr + 1'b1;
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end
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else if (rd_i && !empty_o) begin // FIFO Read
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dat_o <= mem[rd_pntr];
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cntr <= cntr - 1'b1;
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full_o <= 1'b0;
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if (cntr <= 1) begin
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empty_o <= 1'b1;
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cntr <= {fw+2{1'b0}};
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end
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if (rd_pntr >= fl-1)
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rd_pntr <= {fw{1'b0}};
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else
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rd_pntr <= rd_pntr + 1'b1;
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end
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endmodule
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