| Line 63... |
Line 63... |
// RAM BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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`endif
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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clk, ce, we, addr, di, doq
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clk, ce, we, addr, di, doq
|
|
`ifdef OR1200_RAM_PARITY
|
|
, p_err
|
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`endif
|
);
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);
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|
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//
|
//
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// Default address and data buses width
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// Default address and data buses width
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//
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//
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| Line 86... |
Line 89... |
// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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//
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//
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input clk; // Clock
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input clk; // Clock
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input ce; // Chip enable input
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input ce; // Chip enable input
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input we; // Write enable input
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input we; // Write enable input
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//input oe; // Output enable input
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input [aw-1:0] addr; // address bus inputs
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input [aw-1:0] addr; // address bus inputs
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input [dw-1:0] di; // input data bus
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input [dw-1:0] di; // input data bus
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output [dw-1:0] doq; // output data bus
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output [dw-1:0] doq; // output data bus
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`ifdef OR1200_RAM_PARITY
|
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output p_err; // parity error indicator
|
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`endif
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|
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//
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//
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// Internal wires and registers
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// Internal wires and registers
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//
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//
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|
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| Line 102... |
Line 107... |
//
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//
|
|
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//
|
//
|
// Generic RAM's registers and wires
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// Generic RAM's registers and wires
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//
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//
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`ifdef OR1200_GENERIC
|
`ifdef OR1200_RAM_PARITY
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reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [(dw+(dw/8))-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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`else
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`else
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reg [dw-1:0] mem [(1<<aw)-1:0];
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reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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`endif
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`endif
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|
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reg [aw-1:0] addr_reg; // RAM address register
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reg [aw-1:0] addr_reg; // RAM address register
|
|
|
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`ifdef OR1200_RAM_PARITY
|
|
wire [(dw+(dw/8))-1:0] doq_wire;
|
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wire [(dw/8)-1:0] di_p;
|
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wire [(dw/8)-1:0] do_p;
|
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wire [(dw/8)-1:0] parity_err;
|
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`else
|
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wire [dw-1:0] doq_wire;
|
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`endif
|
|
|
|
`ifdef OR1200_RAM_PARITY
|
|
genvar i;
|
|
generate
|
|
for (i=0;i<(dw/8);i=i+1) begin: paritygen
|
|
or1200_parity_gen pgen(.d_i(di[(i*8)+7:(i*8)]), .p_o(di_p[i]));
|
|
or1200_parity_chk pchk(.d_i(doq_wire[(i*8)+7:(i*8)]),
|
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.p_i(do_p[i]), .err_o(parity_err[i]));
|
|
end
|
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endgenerate
|
|
|
|
// Extract parity bits of data out
|
|
assign do_p = doq_wire[(dw+(dw/8))-1:dw];
|
|
|
|
// Indicate error
|
|
assign p_err = (|parity_err);
|
|
|
|
// Inject a parity error. Can specify GPR number to affect,
|
|
// and which parity or data bit to switch.
|
|
task gen_parity_err;
|
|
input [aw-1:0] gpr_no;
|
|
input [31:0] parity_bit_no;
|
|
input [31:0] data_bit_no;
|
|
reg [(dw+(dw/8))-1:0] do_temp;
|
|
begin
|
|
do_temp = mem[gpr_no];
|
|
// Switch parity bit
|
|
if (parity_bit_no > 0 && parity_bit_no <= (dw/8))
|
|
do_temp[dw+(parity_bit_no-1)] = ~do_temp[dw+(parity_bit_no-1)];
|
|
// Switch data bit
|
|
if (data_bit_no > 0 && data_bit_no <= dw)
|
|
do_temp[data_bit_no-1] = ~do_temp[data_bit_no-1];
|
|
// Write word back
|
|
mem[gpr_no] = do_temp;
|
|
end
|
|
endtask // gen_parity_err
|
|
|
|
|
|
`endif
|
|
|
|
|
//
|
//
|
// Data output drivers
|
// Data output drivers
|
//
|
//
|
//assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
|
assign doq_wire = mem[addr_reg];
|
assign doq = mem[addr_reg];
|
assign doq = doq_wire[dw-1:0];
|
|
|
//
|
//
|
// RAM read address register
|
// RAM read address register
|
//
|
//
|
always @(posedge clk)
|
always @(posedge clk)
|
| Line 127... |
Line 182... |
//
|
//
|
// RAM write
|
// RAM write
|
//
|
//
|
always @(posedge clk)
|
always @(posedge clk)
|
if (we && ce)
|
if (we && ce)
|
|
`ifdef OR1200_RAM_PARITY
|
|
mem[addr] <= {di_p,di};
|
|
`else
|
mem[addr] <= di;
|
mem[addr] <= di;
|
|
`endif
|
|
|
endmodule // or1200_spram
|
endmodule // or1200_spram
|
|
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No newline at end of file
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No newline at end of file
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