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Line 62... |
`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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`endif
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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clk, ce, we, addr, di, doq
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clk, rst, ce, we, addr, di, doq
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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, p_err
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, p_err
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`endif
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`endif
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);
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);
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| Line 87... |
Line 87... |
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//
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//
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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//
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//
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input clk; // Clock
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input clk; // Clock
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input rst; // Reset
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input ce; // Chip enable input
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input ce; // Chip enable input
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input we; // Write enable input
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input we; // Write enable input
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input [aw-1:0] addr; // address bus inputs
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input [aw-1:0] addr; // address bus inputs
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input [dw-1:0] di; // input data bus
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input [dw-1:0] di; // input data bus
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output [dw-1:0] doq; // output data bus
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output [dw-1:0] doq; // output data bus
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Line 109... |
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//
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//
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// Generic RAM's registers and wires
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// Generic RAM's registers and wires
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//
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//
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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reg [(dw+(dw/8))-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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parameter par_w = (dw/8);
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reg [(dw+par_w)-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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`else
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`else
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reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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`endif
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`endif
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reg [aw-1:0] addr_reg; // RAM address register
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reg [aw-1:0] addr_reg; // RAM address register
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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wire [(dw+(dw/8))-1:0] doq_wire;
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wire [(dw+par_w)-1:0] doq_wire;
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wire [(dw/8)-1:0] di_p;
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wire [par_w-1:0] di_p;
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wire [(dw/8)-1:0] do_p;
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wire [par_w-1:0] do_p;
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wire [(dw/8)-1:0] parity_err;
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wire [par_w-1:0] parity_err;
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reg ce_r;
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`else
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`else
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wire [dw-1:0] doq_wire;
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wire [dw-1:0] doq_wire;
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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genvar i;
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genvar i;
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generate
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generate
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for (i=0;i<(dw/8);i=i+1) begin: paritygen
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for (i=0;i<par_w;i=i+1) begin: paritygen
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or1200_parity_gen pgen(.d_i(di[(i*8)+7:(i*8)]), .p_o(di_p[i]));
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or1200_parity_gen pgen(.d_i(di[(i*8)+7:(i*8)]), .p_o(di_p[i]));
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or1200_parity_chk pchk(.d_i(doq_wire[(i*8)+7:(i*8)]),
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or1200_parity_chk pchk(.d_i(doq_wire[(i*8)+7:(i*8)]),
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.p_i(do_p[i]), .err_o(parity_err[i]));
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.p_i(do_p[i]), .err_o(parity_err[i]));
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end
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end
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endgenerate
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endgenerate
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// Extract parity bits of data out
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// Extract parity bits of data out
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assign do_p = doq_wire[(dw+(dw/8))-1:dw];
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assign do_p = doq_wire[(dw+par_w)-1:dw];
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always @(posedge clk)
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if (rst)
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ce_r <= 0;
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else
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ce_r <= ce;
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// Indicate error
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// Indicate error
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assign p_err = (|parity_err);
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assign p_err = (|parity_err) & ce_r;
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// Inject a parity error. Can specify GPR number to affect,
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// Inject a parity error.
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// and which parity or data bit to switch.
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task gen_parity_err;
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task gen_parity_err;
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input [aw-1:0] gpr_no;
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input [aw-1:0] addr;
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input [31:0] parity_bit_no;
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input [31:0] parity_bit_no;
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input [31:0] data_bit_no;
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input [31:0] data_bit_no;
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reg [(dw+(dw/8))-1:0] do_temp;
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reg [(dw+par_w)-1:0] do_temp;
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begin
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begin
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do_temp = mem[gpr_no];
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do_temp = mem[addr];
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// Switch parity bit
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// Switch parity bit
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if (parity_bit_no > 0 && parity_bit_no <= (dw/8))
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if (parity_bit_no >= 0 && parity_bit_no < par_w)
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do_temp[dw+(parity_bit_no-1)] = ~do_temp[dw+(parity_bit_no-1)];
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do_temp[dw+parity_bit_no] = ~do_temp[dw+parity_bit_no];
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// Switch data bit
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// Switch data bit
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if (data_bit_no > 0 && data_bit_no <= dw)
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if (data_bit_no >= 0 && data_bit_no < dw)
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do_temp[data_bit_no-1] = ~do_temp[data_bit_no-1];
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do_temp[data_bit_no] = ~do_temp[data_bit_no];
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// Write word back
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// Write word back
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mem[gpr_no] = do_temp;
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mem[addr] = do_temp;
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end
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end
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endtask // gen_parity_err
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endtask // gen_parity_err
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`endif
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`endif
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//
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//
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// Data output drivers
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// Data output drivers
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Line 187... |
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//
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//
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// RAM write
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// RAM write
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//
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//
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always @(posedge clk)
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always @(posedge clk)
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if (we && ce)
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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if (we && ce)
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mem[addr] <= {di_p,di};
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mem[addr] <= {di_p,di};
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`else
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`else
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if (we && ce)
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mem[addr] <= di;
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mem[addr] <= di;
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`endif
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`endif
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endmodule // or1200_spram
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endmodule // or1200_spram
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