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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Generic Single-Port Synchronous RAM with byte write signals ////
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//// ////
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//// This file is part of memory library available from ////
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//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
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//// ////
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//// Description ////
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//// This block is a wrapper with common single-port ////
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//// synchronous memory interface for different ////
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//// types of ASIC and FPGA RAMs. Beside universal memory ////
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//// interface it also provides behavioral model of generic ////
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//// single-port synchronous RAM. ////
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//// It should be used in all OPENCORES designs that want to be ////
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//// portable accross different target technologies and ////
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//// independent of target memory. ////
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//// ////
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//// Supported ASIC RAMs are: ////
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//// - Artisan Single-Port Sync RAM ////
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//// - Avant! Two-Port Sync RAM (*) ////
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//// - Virage Single-Port Sync RAM ////
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//// - Virtual Silicon Single-Port Sync RAM ////
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//// ////
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//// Supported FPGA RAMs are: ////
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//// - Xilinx Virtex RAMB16 ////
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//// - Xilinx Virtex RAMB4 ////
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//// ////
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//// To Do: ////
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//// - xilinx rams need external tri-state logic ////
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//// - fix avant! two-port ram ////
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//// - add additional RAMs ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: or1200_spram_2048x32_bw.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Coding style changed.
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//
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// Revision 1.5 2005/10/19 11:37:56 jcastillo
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// Added support for RAMB16 Xilinx4/Spartan3 primitives
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//
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// Revision 1.4 2004/06/08 18:15:32 lampret
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// Changed behavior of the simulation generic models
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//
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// Revision 1.3 2003/10/17 07:59:44 markom
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// mbist signals updated according to newest convention
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//
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// Revision 1.2 2003/09/12 09:03:54 dries
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// correct all the syntax errors
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//
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// Revision 1.1 2003/08/26 09:37:02 simons
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// Added support for rams with byte write access.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_spram_2048x32_bw(
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`ifdef OR1200_BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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// Generic synchronous single-port RAM interface
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clk, rst, ce, we, oe, addr, di, doq
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);
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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output mbist_so_o;
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`endif
|
|
|
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//
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// Generic synchronous single-port RAM interface
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//
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input clk; // Clock
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input rst; // Reset
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input ce; // Chip enable input
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input [3:0] we; // Write enable input
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input oe; // Output enable input
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input [10:0] addr; // address bus inputs
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input [31:0] di; // input data bus
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output [31:0] doq; // output data bus
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//
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// Internal wires and registers
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//
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`ifdef OR1200_ARTISAN_SSP
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`else
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`ifdef OR1200_VIRTUALSILICON_SSP
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`else
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`ifdef OR1200_BIST
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assign mbist_so_o = mbist_si_i;
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`endif
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`endif
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`endif
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|
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`ifdef OR1200_ARTISAN_SSP
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//
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// Instantiation of ASIC memory:
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//
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// Artisan Synchronous Single-Port RAM (ra1sh)
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//
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`ifdef UNUSED
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art_hssp_2048x32_bw artisan_ssp(
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`else
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`ifdef OR1200_BIST
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art_hssp_2048x32_bw_bist artisan_ssp(
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`else
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art_hssp_2048x32_bw artisan_ssp(
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`endif
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`endif
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`ifdef OR1200_BIST
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// RAM BIST
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.mbist_si_i(mbist_si_i),
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.mbist_so_o(mbist_so_o),
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.mbist_ctrl_i(mbist_ctrl_i),
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`endif
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.CLK(clk),
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.CEN(~ce),
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.WEN(~we),
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.A(addr),
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.D(di),
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.OEN(~oe),
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.Q(doq)
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);
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`else
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`ifdef OR1200_AVANT_ATP
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//
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// Instantiation of ASIC memory:
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//
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// Avant! Asynchronous Two-Port RAM
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//
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avant_atp avant_atp(
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.web(~we),
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.reb(),
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.oeb(~oe),
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.rcsb(),
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.wcsb(),
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.ra(addr),
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.wa(addr),
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.di(di),
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.doq(doq)
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|
);
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`else
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`ifdef OR1200_VIRAGE_SSP
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//
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|
// Instantiation of ASIC memory:
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|
//
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|
// Virage Synchronous 1-port R/W RAM
|
|
//
|
|
virage_ssp virage_ssp(
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.clk(clk),
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.adr(addr),
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.d(di),
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.we(we),
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.oe(oe),
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.me(ce),
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|
.q(doq)
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|
);
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|
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`else
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|
|
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`ifdef OR1200_VIRTUALSILICON_SSP
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|
|
|
//
|
|
// Instantiation of ASIC memory:
|
|
//
|
|
// Virtual Silicon Single-Port Synchronous SRAM
|
|
//
|
|
`ifdef OR1200_BIST
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|
wire mbist_si_i_ram_0;
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wire mbist_si_i_ram_1;
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wire mbist_si_i_ram_2;
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wire mbist_si_i_ram_3;
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wire mbist_so_o_ram_0;
|
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wire mbist_so_o_ram_1;
|
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wire mbist_so_o_ram_2;
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wire mbist_so_o_ram_3;
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assign mbist_si_i_ram_0 = mbist_si_i;
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assign mbist_si_i_ram_1 = mbist_so_o_ram_0;
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assign mbist_si_i_ram_2 = mbist_so_o_ram_1;
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assign mbist_si_i_ram_3 = mbist_so_o_ram_2;
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assign mbist_so_o = mbist_so_o_ram_3;
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`endif
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|
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`ifdef UNUSED
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|
vs_hdsp_2048x8 vs_ssp_0(
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`else
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|
`ifdef OR1200_BIST
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vs_hdsp_2048x8_bist vs_ssp_0(
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`else
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vs_hdsp_2048x8 vs_ssp_0(
|
|
`endif
|
|
`endif
|
|
`ifdef OR1200_BIST
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|
// RAM BIST
|
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.mbist_si_i(mbist_si_i_ram_0),
|
|
.mbist_so_o(mbist_so_o_ram_0),
|
|
.mbist_ctrl_i(mbist_ctrl_i),
|
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`endif
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.CK(clk),
|
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.ADR(addr),
|
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.DI(di[7:0]),
|
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.WEN(~we[0]),
|
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.CEN(~ce),
|
|
.OEN(~oe),
|
|
.DOUT(doq[7:0])
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|
);
|
|
|
|
`ifdef UNUSED
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|
vs_hdsp_2048x8 vs_ssp_1(
|
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`else
|
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`ifdef OR1200_BIST
|
|
vs_hdsp_2048x8_bist vs_ssp_1(
|
|
`else
|
|
vs_hdsp_2048x8 vs_ssp_1(
|
|
`endif
|
|
`endif
|
|
`ifdef OR1200_BIST
|
|
// RAM BIST
|
|
.mbist_si_i(mbist_si_i_ram_1),
|
|
.mbist_so_o(mbist_so_o_ram_1),
|
|
.mbist_ctrl_i(mbist_ctrl_i),
|
|
`endif
|
|
.CK(clk),
|
|
.ADR(addr),
|
|
.DI(di[15:8]),
|
|
.WEN(~we[1]),
|
|
.CEN(~ce),
|
|
.OEN(~oe),
|
|
.DOUT(doq[15:8])
|
|
);
|
|
|
|
`ifdef UNUSED
|
|
vs_hdsp_2048x8 vs_ssp_2(
|
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`else
|
|
`ifdef OR1200_BIST
|
|
vs_hdsp_2048x8_bist vs_ssp_2(
|
|
`else
|
|
vs_hdsp_2048x8 vs_ssp_2(
|
|
`endif
|
|
`endif
|
|
`ifdef OR1200_BIST
|
|
// RAM BIST
|
|
.mbist_si_i(mbist_si_i_ram_2),
|
|
.mbist_so_o(mbist_so_o_ram_2),
|
|
.mbist_ctrl_i(mbist_ctrl_i),
|
|
`endif
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|
.CK(clk),
|
|
.ADR(addr),
|
|
.DI(di[23:16]),
|
|
.WEN(~we[2]),
|
|
.CEN(~ce),
|
|
.OEN(~oe),
|
|
.DOUT(doq[23:16])
|
|
);
|
|
|
|
`ifdef UNUSED
|
|
vs_hdsp_2048x8 vs_ssp_3(
|
|
`else
|
|
`ifdef OR1200_BIST
|
|
vs_hdsp_2048x8_bist vs_ssp_3(
|
|
`else
|
|
vs_hdsp_2048x8 vs_ssp_3(
|
|
`endif
|
|
`endif
|
|
`ifdef OR1200_BIST
|
|
// RAM BIST
|
|
.mbist_si_i(mbist_si_i_ram_3),
|
|
.mbist_so_o(mbist_so_o_ram_3),
|
|
.mbist_ctrl_i(mbist_ctrl_i),
|
|
`endif
|
|
.CK(clk),
|
|
.ADR(addr),
|
|
.DI(di[31:24]),
|
|
.WEN(~we[3]),
|
|
.CEN(~ce),
|
|
.OEN(~oe),
|
|
.DOUT(doq[31:24])
|
|
);
|
|
|
|
`else
|
|
|
|
`ifdef OR1200_XILINX_RAMB4
|
|
|
|
//
|
|
// Instantiation of FPGA memory:
|
|
//
|
|
// Virtex/Spartan2
|
|
//
|
|
|
|
//
|
|
// Block 0
|
|
//
|
|
RAMB4_S2 ramb4_s2_0(
|
|
.CLK(clk),
|
|
.RST(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[1:0]),
|
|
.EN(ce),
|
|
.WE(we[0]),
|
|
.DO(doq[1:0])
|
|
);
|
|
|
|
//
|
|
// Block 1
|
|
//
|
|
RAMB4_S2 ramb4_s2_1(
|
|
.CLK(clk),
|
|
.RST(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[3:2]),
|
|
.EN(ce),
|
|
.WE(we[0]),
|
|
.DO(doq[3:2])
|
|
);
|
|
|
|
//
|
|
// Block 2
|
|
//
|
|
RAMB4_S2 ramb4_s2_2(
|
|
.CLK(clk),
|
|
.RST(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[5:4]),
|
|
.EN(ce),
|
|
.WE(we[0]),
|
|
.DO(doq[5:4])
|
|
);
|
|
|
|
//
|
|
// Block 3
|
|
//
|
|
RAMB4_S2 ramb4_s2_3(
|
|
.CLK(clk),
|
|
.RST(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[7:6]),
|
|
.EN(ce),
|
|
.WE(we[0]),
|
|
.DO(doq[7:6])
|
|
);
|
|
//
|
|
// Block 4
|
|
//
|
|
RAMB4_S2 ramb4_s2_4(
|
|
.CLK(clk),
|
|
.RST(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[9:8]),
|
|
.EN(ce),
|
|
.WE(we[1]),
|
|
.DO(doq[9:8])
|
|
);
|
|
|
|
//
|
|
// Block 5
|
|
//
|
|
RAMB4_S2 ramb4_s2_5(
|
|
.CLK(clk),
|
|
.RST(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[11:10]),
|
|
.EN(ce),
|
|
.WE(we[1]),
|
|
.DO(doq[11:10])
|
|
);
|
|
|
|
//
|
|
// Block 6
|
|
//
|
|
RAMB4_S2 ramb4_s2_6(
|
|
.CLK(clk),
|
|
.RST(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[13:12]),
|
|
.EN(ce),
|
|
.WE(we[1]),
|
|
.DO(doq[13:12])
|
|
);
|
|
|
|
//
|
|
// Block 7
|
|
//
|
|
RAMB4_S2 ramb4_s2_7(
|
|
.CLK(clk),
|
|
.RST(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[15:14]),
|
|
.EN(ce),
|
|
.WE(we[1]),
|
|
.DO(doq[15:14])
|
|
);
|
|
//
|
|
// Block 8
|
|
//
|
|
RAMB4_S2 ramb4_s2_8(
|
|
.CLK(clk),
|
|
.RST(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[17:16]),
|
|
.EN(ce),
|
|
.WE(we[2]),
|
|
.DO(doq[17:16])
|
|
);
|
|
|
|
//
|
|
// Block 9
|
|
//
|
|
RAMB4_S2 ramb4_s2_9(
|
|
.CLK(clk),
|
|
.RST(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[19:18]),
|
|
.EN(ce),
|
|
.WE(we[2]),
|
|
.DO(doq[19:18])
|
|
);
|
|
|
|
//
|
|
// Block 10
|
|
//
|
|
RAMB4_S2 ramb4_s2_10(
|
|
.CLK(clk),
|
|
.RST(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[21:20]),
|
|
.EN(ce),
|
|
.WE(we[2]),
|
|
.DO(doq[21:20])
|
|
);
|
|
|
|
//
|
|
// Block 11
|
|
//
|
|
RAMB4_S2 ramb4_s2_11(
|
|
.CLK(clk),
|
|
.RST(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[23:22]),
|
|
.EN(ce),
|
|
.WE(we[2]),
|
|
.DO(doq[23:22])
|
|
);
|
|
//
|
|
// Block 12
|
|
//
|
|
RAMB4_S2 ramb4_s2_12(
|
|
.CLK(clk),
|
|
.RST(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[25:24]),
|
|
.EN(ce),
|
|
.WE(we[3]),
|
|
.DO(doq[25:24])
|
|
);
|
|
|
|
//
|
|
// Block 13
|
|
//
|
|
RAMB4_S2 ramb4_s2_13(
|
|
.CLK(clk),
|
|
.RST(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[27:26]),
|
|
.EN(ce),
|
|
.WE(we[3]),
|
|
.DO(doq[27:26])
|
|
);
|
|
|
|
//
|
|
// Block 14
|
|
//
|
|
RAMB4_S2 ramb4_s2_14(
|
|
.CLK(clk),
|
|
.RST(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[29:28]),
|
|
.EN(ce),
|
|
.WE(we[3]),
|
|
.DO(doq[29:28])
|
|
);
|
|
|
|
//
|
|
// Block 15
|
|
//
|
|
RAMB4_S2 ramb4_s2_15(
|
|
.CLK(clk),
|
|
.RST(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[31:30]),
|
|
.EN(ce),
|
|
.WE(we[3]),
|
|
.DO(doq[31:30])
|
|
);
|
|
|
|
`else
|
|
|
|
`ifdef OR1200_XILINX_RAMB16
|
|
|
|
//
|
|
// Instantiation of FPGA memory:
|
|
//
|
|
// Virtex4/Spartan3E
|
|
//
|
|
// Added By Nir Mor
|
|
//
|
|
|
|
//
|
|
// Block 0
|
|
//
|
|
RAMB16_S9 ramb16_s9_0(
|
|
.CLK(clk),
|
|
.SSR(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[7:0]),
|
|
.DIP(1'b0),
|
|
.EN(ce),
|
|
.WE(we[0]),
|
|
.DO(doq[7:0]),
|
|
.DOP()
|
|
);
|
|
|
|
//
|
|
// Block 1
|
|
//
|
|
RAMB16_S9 ramb16_s9_1(
|
|
.CLK(clk),
|
|
.SSR(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[15:8]),
|
|
.DIP(1'b0),
|
|
.EN(ce),
|
|
.WE(we[1]),
|
|
.DO(doq[15:8]),
|
|
.DOP()
|
|
);
|
|
|
|
//
|
|
// Block 2
|
|
//
|
|
RAMB16_S9 ramb16_s9_2(
|
|
.CLK(clk),
|
|
.SSR(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[23:16]),
|
|
.DIP(1'b0),
|
|
.EN(ce),
|
|
.WE(we[2]),
|
|
.DO(doq[23:16]),
|
|
.DOP()
|
|
);
|
|
|
|
//
|
|
// Block 3
|
|
//
|
|
RAMB16_S9 ramb16_s9_3(
|
|
.CLK(clk),
|
|
.SSR(1'b0),
|
|
.ADDR(addr),
|
|
.DI(di[31:24]),
|
|
.DIP(1'b0),
|
|
.EN(ce),
|
|
.WE(we[3]),
|
|
.DO(doq[31:24]),
|
|
.DOP()
|
|
);
|
|
|
|
`else
|
|
|
|
//
|
|
// Generic single-port synchronous RAM model
|
|
//
|
|
|
|
//
|
|
// Generic RAM's registers and wires
|
|
//
|
|
reg [7:0] mem_0 [2047:0]; // RAM content
|
|
reg [7:0] mem_1 [2047:0]; // RAM content
|
|
reg [7:0] mem_2 [2047:0]; // RAM content
|
|
reg [7:0] mem_3 [2047:0]; // RAM content
|
|
reg [10:0] addr_reg; // RAM address register
|
|
|
|
//
|
|
// Data output drivers
|
|
//
|
|
assign doq = (oe) ? {mem_3[addr_reg], mem_2[addr_reg], mem_1[addr_reg], mem_0[addr_reg]} : {32{1'b0}};
|
|
|
|
//
|
|
// RAM address register
|
|
//
|
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
|
if (rst == `OR1200_RST_VALUE)
|
|
addr_reg <= 11'h000;
|
|
else if (ce)
|
|
addr_reg <= addr;
|
|
|
|
//
|
|
// RAM write byte 0
|
|
//
|
|
always @(posedge clk)
|
|
if (ce && we[0])
|
|
mem_0[addr] <= di[7:0];
|
|
|
|
//
|
|
// RAM write byte 1
|
|
//
|
|
always @(posedge clk)
|
|
if (ce && we[1])
|
|
mem_1[addr] <= di[15:8];
|
|
|
|
//
|
|
// RAM write byte 2
|
|
//
|
|
always @(posedge clk)
|
|
if (ce && we[2])
|
|
mem_2[addr] <= di[23:16];
|
|
|
|
//
|
|
// RAM write byte 3
|
|
//
|
|
always @(posedge clk)
|
|
if (ce && we[3])
|
|
mem_3[addr] <= di[31:24];
|
|
|
|
`endif // !OR1200_XILINX_RAMB16
|
|
`endif // !OR1200_XILINX_RAMB4
|
|
`endif // !OR1200_VIRTUALSILICON_SSP
|
|
`endif // !OR1200_VIRAGE_SSP
|
|
`endif // !OR1200_AVANT_ATP
|
|
`endif // !OR1200_ARTISAN_SSP
|
|
|
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
