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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_spram_32_bw.v] - Diff between revs 482 and 483

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Rev 482 Rev 483
Line 63... Line 63... 
`ifdef OR1200_BIST
 
`ifdef OR1200_BIST
 
   // RAM BIST
 
   // RAM BIST
 
   mbist_si_i, mbist_so_o, mbist_ctrl_i,
 
   mbist_si_i, mbist_so_o, mbist_ctrl_i,
 
`endif
 
`endif
 
   // Generic synchronous single-port RAM interface
 
   // Generic synchronous single-port RAM interface
 
   clk, ce, we, addr, di, doq
 
   clk, rst, ce, we, addr, di, doq
 
`ifdef OR1200_RAM_PARITY
 
`ifdef OR1200_RAM_PARITY
 
   , p_err
 
   , p_err
 
`endif
 
`endif
 
   );
 
   );
 
 
 
 
Line 87... Line 87... 
   input mbist_si_i;
 
   input mbist_si_i;
 
   input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
 
   input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
 
   output                                 mbist_so_o;
 
   output                                 mbist_so_o;
 
`endif
 
`endif
 
 
 
 
 
 
 
`ifdef OR1200_RAM_PARITY
 
 
 
   output                                 p_err; // parity error indicator
 
 
 
`endif
 
 
 
 
 
   //
 
   //
 
   // Generic synchronous single-port RAM interface
 
   // Generic synchronous single-port byte-writable RAM interface
 
   //
 
   //
 
   input                                  clk;  // Clock
 
   input                                  clk;  // Clock
 
 
 
   input                                  rst;  // Reset
 
   input                                  ce;   // Chip enable input
 
   input                                  ce;   // Chip enable input
 
   input [3:0]                             we;   // Write enable input
 
   input [3:0]                             we;   // Write enable input
 
   input [aw-1:0]                          addr; // address bus inputs
 
   input [aw-1:0]                          addr; // address bus inputs
 
   input [dw-1:0]                          di;   // input data bus
 
   input [dw-1:0]                          di;   // input data bus
 
   output [dw-1:0]                         doq;  // output data bus
 
   output [dw-1:0]                         doq;  // output data bus
 
`ifdef OR1200_RAM_PARITY
 
 
 
   output                                 p_err; // parity error indicator
 
 
 
`endif
 
 
 
 
 
 
 
   //
 
   //
 
   // Internal wires and registers
 
   // Internal wires and registers
 
   //
 
   //
 
 
 
 
Line 133... Line 136... 
   wire [bw:0]                             doq2_wire;
 
   wire [bw:0]                             doq2_wire;
 
   wire [bw:0]                             doq3_wire;
 
   wire [bw:0]                             doq3_wire;
 
   wire [(dw/8)-1:0]                       di_p;
 
   wire [(dw/8)-1:0]                       di_p;
 
   wire [(dw/8)-1:0]                       do_p;
 
   wire [(dw/8)-1:0]                       do_p;
 
   wire [(dw/8)-1:0]                       parity_err;
 
   wire [(dw/8)-1:0]                       parity_err;
 
 
 
   reg                                    ce_r;
 
`else
 
`else
 
   wire [dw-1:0]                           doq_wire;
 
   wire [dw-1:0]                           doq_wire;
 
`endif
 
`endif
 
 
 
 
 
`ifdef OR1200_RAM_PARITY
 
`ifdef OR1200_RAM_PARITY
Line 150... Line 154... 
   endgenerate
 
   endgenerate
 
 
 
 
 
   // Extract parity bits of data out
 
   // Extract parity bits of data out
 
   assign do_p = doq_wire[(dw+(dw/8))-1:dw];
 
   assign do_p = doq_wire[(dw+(dw/8))-1:dw];
 
 
 
 
 
 
 
   always @(posedge clk)
 
 
 
     if (rst)
 
 
 
       ce_r <= 0;
 
 
 
     else
 
 
 
       ce_r <= ce;
 
 
 
 
 
   // Indicate error
 
   // Indicate error
 
   assign p_err = (|parity_err);
 
   assign p_err = (|parity_err) & ce_r;
 
 
 
 
 
   // Inject a parity error. Can specify GPR number to affect,
 
   // Inject a parity error. Can specify GPR number to affect,
 
   // and which parity or data bit to switch.
 
   // and which parity or data bit to switch.
 
   task gen_parity_err;
 
   task gen_parity_err;
 
      input [aw-1:0]             gpr_no;
 
      input [aw-1:0]             word_no;
 
      input [31:0]               parity_bit_no;
 
 
 
      input [31:0]               data_bit_no;
 
      input [31:0]               data_bit_no;
 
      reg [(dw+(dw/8))-1:0]      do_temp;
 
      reg [bw:0]                 do_temp;
 
      begin
 
      begin
 
         // TODO
 
         // Fish word out
 
         /*
 
         if (data_bit_no < 8) begin
 
         do_temp = mem[gpr_no];
 
            do_temp = mem0[word_no];
 
         // Switch parity bit
 
         end
 
         if (parity_bit_no > 0 && parity_bit_no <= (dw/8))
 
         else if (data_bit_no < 16) begin
 
           do_temp[dw+(parity_bit_no-1)] = ~do_temp[dw+(parity_bit_no-1)];
 
            do_temp = mem1[word_no];
 
         // Switch data bit
 
            data_bit_no = data_bit_no - 8;
 
         if (data_bit_no > 0 && data_bit_no <= dw)
 
         end
 
           do_temp[data_bit_no-1] = ~do_temp[data_bit_no-1];
 
         else if (data_bit_no < 24) begin
 
         // Write word back
 
            do_temp = mem2[word_no];
 
         mem[gpr_no] = do_temp;
 
            data_bit_no = data_bit_no - 16;
 
          */
 
         end
 
 
 
         else if (data_bit_no < 32) begin
 
 
 
            do_temp = mem3[word_no];
 
 
 
            data_bit_no = data_bit_no - 24;
 
 
 
         end
 
 
 
         else begin
 
 
 
            do_temp = mem3[word_no];
 
 
 
            data_bit_no = 8;
 
 
 
         end
 
 
 
 
 
 
 
         // Switch bit
 
 
 
         do_temp[data_bit_no] = ~do_temp[data_bit_no] ;
 
 
 
 
 
 
 
         // Replace word
 
 
 
         if (data_bit_no < 8)
 
 
 
            mem0[word_no] = do_temp;
 
 
 
         else if (data_bit_no < 16)
 
 
 
            mem1[word_no] = do_temp;
 
 
 
         else if (data_bit_no < 24)
 
 
 
           mem2[word_no] = do_temp;
 
 
 
         else
 
 
 
            mem3[word_no] = do_temp;
 
      end
 
      end
 
   endtask // gen_parity_err
 
   endtask // gen_parity_err
 
`endif
 
`endif
 
 
 
 
 
   //
 
   //
Line 230... Line 260... 
        if (we[0])
 
        if (we[0])
 
          mem3[addr] <=  di[(bw*0)+(bw-1):(bw*0)];
 
          mem3[addr] <=  di[(bw*0)+(bw-1):(bw*0)];
 
`endif
 
`endif
 
     end
 
     end
 
 
 
 
 
endmodule // or1200_spram
 
endmodule // or1200_spram_32_bw
 
 
 
 
 
 
 
 
 
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