| Line 55... |
Line 55... |
// Clk & Rst
|
// Clk & Rst
|
clk, rst,
|
clk, rst,
|
|
|
// Internal CPU interface
|
// Internal CPU interface
|
flagforw, flag_we, flag, cyforw, cy_we, carry,
|
flagforw, flag_we, flag, cyforw, cy_we, carry,
|
addrbase, addrofs, dat_i, branch_op, ex_spr_read, ex_spr_write,
|
addrbase, addrofs, dat_i, branch_op, ex_spr_read,
|
|
ex_spr_write,
|
epcr, eear, esr, except_started,
|
epcr, eear, esr, except_started,
|
to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
|
to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
|
spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
|
spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc,
|
|
spr_dat_mac,
|
|
|
boot_adr_sel_i,
|
boot_adr_sel_i,
|
|
|
// Floating point SPR input
|
// Floating point SPR input
|
fpcsr, fpcsr_we, spr_dat_fpu,
|
fpcsr, fpcsr_we, spr_dat_fpu,
|
|
|
| Line 163... |
Line 166... |
wire eear_sel; // Select for EEAR0
|
wire eear_sel; // Select for EEAR0
|
wire esr_sel; // Select for ESR0
|
wire esr_sel; // Select for ESR0
|
wire fpcsr_sel; // Select for FPCSR
|
wire fpcsr_sel; // Select for FPCSR
|
wire [31:0] sys_data; // Read data from system SPRs
|
wire [31:0] sys_data; // Read data from system SPRs
|
wire du_access; // Debug unit access
|
wire du_access; // Debug unit access
|
reg [31:0] unqualified_cs; // Unqualified chip selects
|
reg [31:0] unqualified_cs; // Unqualified selects
|
wire ex_spr_write; // jb
|
wire ex_spr_write; // jb
|
|
|
//
|
//
|
// Decide if it is debug unit access
|
// Decide if it is debug unit access
|
//
|
//
|
| Line 199... |
Line 202... |
|
|
|
|
//
|
//
|
// Qualify chip selects
|
// Qualify chip selects
|
//
|
//
|
assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read | (ex_spr_write & sr[`OR1200_SR_SM])}};
|
assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read |
|
|
(ex_spr_write & sr[`OR1200_SR_SM])}};
|
|
|
//
|
//
|
// Decoding of groups
|
// Decoding of groups
|
//
|
//
|
always @(spr_addr)
|
always @(spr_addr)
|
case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
|
case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
|
`OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
|
`OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
|
= 32'b00000000_00000000_00000000_00000001;
|
`OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
|
`OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
|
= 32'b00000000_00000000_00000000_00000010;
|
`OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
|
`OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
|
= 32'b00000000_00000000_00000000_00000100;
|
`OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
|
`OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
|
= 32'b00000000_00000000_00000000_00001000;
|
`OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
|
= 32'b00000000_00000000_00000000_00010000;
|
`OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
|
= 32'b00000000_00000000_00000000_00100000;
|
`OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
|
= 32'b00000000_00000000_00000000_01000000;
|
`OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
|
= 32'b00000000_00000000_00000000_10000000;
|
`OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
|
= 32'b00000000_00000000_00000001_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
|
= 32'b00000000_00000000_00000010_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
|
= 32'b00000000_00000000_00000100_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
|
= 32'b00000000_00000000_00001000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
|
= 32'b00000000_00000000_00010000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
|
= 32'b00000000_00000000_00100000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
|
= 32'b00000000_00000000_01000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
|
= 32'b00000000_00000000_10000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs
|
|
= 32'b00000000_00000001_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs
|
|
= 32'b00000000_00000010_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs
|
|
= 32'b00000000_00000100_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs
|
|
= 32'b00000000_00001000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs
|
|
= 32'b00000000_00010000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs
|
|
= 32'b00000000_00100000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs
|
|
= 32'b00000000_01000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs
|
|
= 32'b00000000_10000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs
|
|
= 32'b00000001_00000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs
|
|
= 32'b00000010_00000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs
|
|
= 32'b00000100_00000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs
|
|
= 32'b00001000_00000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs
|
|
= 32'b00010000_00000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs
|
|
= 32'b00100000_00000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs
|
|
= 32'b01000000_00000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs
|
|
= 32'b10000000_00000000_00000000_00000000;
|
endcase
|
endcase
|
|
|
//
|
//
|
// SPRs System Group
|
// SPRs System Group
|
//
|
//
|
|
|
//
|
//
|
// What to write into SR
|
// What to write into SR
|
//
|
//
|
assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] =
|
assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV]
|
(except_started) ? sr[`OR1200_SR_FO:`OR1200_SR_OV] :
|
= (except_started) ? sr[`OR1200_SR_FO:`OR1200_SR_OV] :
|
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] :
|
(branch_op == `OR1200_BRANCHOP_RFE) ?
|
(spr_we && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
|
esr[`OR1200_SR_FO:`OR1200_SR_OV] : (spr_we && sr_sel) ?
|
|
{1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]} :
|
sr[`OR1200_SR_FO:`OR1200_SR_OV];
|
sr[`OR1200_SR_FO:`OR1200_SR_OV];
|
assign to_sr[`OR1200_SR_TED] =
|
assign to_sr[`OR1200_SR_TED]
|
(except_started) ? 1'b1 :
|
= (except_started) ? 1'b1 :
|
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
|
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
|
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED]:
|
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED]:
|
sr[`OR1200_SR_TED];
|
sr[`OR1200_SR_TED];
|
assign to_sr[`OR1200_SR_CY] =
|
|
(except_started) ? sr[`OR1200_SR_CY] :
|
assign to_sr[`OR1200_SR_CY]
|
|
= (except_started) ? sr[`OR1200_SR_CY] :
|
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
|
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
|
cy_we ? cyforw :
|
cy_we ? cyforw :
|
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
|
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
|
sr[`OR1200_SR_CY];
|
sr[`OR1200_SR_CY];
|
assign to_sr[`OR1200_SR_F] =
|
assign to_sr[`OR1200_SR_F]
|
(except_started) ? sr[`OR1200_SR_F] :
|
= (except_started) ? sr[`OR1200_SR_F] :
|
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
|
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
|
flag_we ? flagforw :
|
flag_we ? flagforw :
|
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
|
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
|
sr[`OR1200_SR_F];
|
sr[`OR1200_SR_F];
|
assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] =
|
|
(except_started) ? {sr[`OR1200_SR_CE:`OR1200_SR_LEE], 2'b00, sr[`OR1200_SR_ICE:`OR1200_SR_DCE], 3'b001} :
|
assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM]
|
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] :
|
= (except_started) ? {sr[`OR1200_SR_CE:`OR1200_SR_LEE], 2'b00,
|
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
|
sr[`OR1200_SR_ICE:`OR1200_SR_DCE], 3'b001} :
|
|
(branch_op == `OR1200_BRANCHOP_RFE) ?
|
|
esr[`OR1200_SR_CE:`OR1200_SR_SM] : (spr_we && sr_sel) ?
|
|
spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM] :
|
sr[`OR1200_SR_CE:`OR1200_SR_SM];
|
sr[`OR1200_SR_CE:`OR1200_SR_SM];
|
|
|
//
|
//
|
// Selects for system SPRs
|
// Selects for system SPRs
|
//
|
//
|
assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
|
assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF));
|
(spr_addr[10:4] == `OR1200_SPR_CFGR));
|
assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC));
|
assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
|
(spr_addr[10:5] == `OR1200_SPR_RF));
|
assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
|
assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
|
(spr_addr[10:0] == `OR1200_SPR_NPC));
|
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
|
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
|
(spr_addr[10:0] == `OR1200_SPR_PPC));
|
assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_FPCSR));
|
assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
|
(spr_addr[10:0] == `OR1200_SPR_SR));
|
|
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
|
(spr_addr[10:0] == `OR1200_SPR_EPCR));
|
|
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
|
(spr_addr[10:0] == `OR1200_SPR_EEAR));
|
|
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
|
(spr_addr[10:0] == `OR1200_SPR_ESR));
|
|
assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
|
(spr_addr[10:0] == `OR1200_SPR_FPCSR));
|
|
|
|
|
//
|
//
|
// Write enables for system SPRs
|
// Write enables for system SPRs
|
//
|
//
|
assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
|
assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) |
|
|
flag_we | cy_we;
|
assign pc_we = (du_write && (npc_sel | ppc_sel));
|
assign pc_we = (du_write && (npc_sel | ppc_sel));
|
assign epcr_we = (spr_we && epcr_sel);
|
assign epcr_we = (spr_we && epcr_sel);
|
assign eear_we = (spr_we && eear_sel);
|
assign eear_we = (spr_we && eear_sel);
|
assign esr_we = (spr_we && esr_sel);
|
assign esr_we = (spr_we && esr_sel);
|
assign fpcsr_we = (spr_we && fpcsr_sel);
|
assign fpcsr_we = (spr_we && fpcsr_sel);
|
| Line 309... |
Line 360... |
(spr_dat_npc & {32{npc_sel}}) |
|
(spr_dat_npc & {32{npc_sel}}) |
|
(spr_dat_ppc & {32{ppc_sel}}) |
|
(spr_dat_ppc & {32{ppc_sel}}) |
|
({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
|
({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
|
(epcr & {32{epcr_sel}}) |
|
(epcr & {32{epcr_sel}}) |
|
(eear & {32{eear_sel}}) |
|
(eear & {32{eear_sel}}) |
|
({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} & {32{fpcsr_sel}}) |
|
({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} &
|
|
{32{fpcsr_sel}}) |
|
({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
|
({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
|
|
|
//
|
//
|
// Flag alias
|
// Flag alias
|
//
|
//
|
| Line 327... |
Line 379... |
//
|
//
|
// Supervision register
|
// Supervision register
|
//
|
//
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
if (rst == `OR1200_RST_VALUE)
|
if (rst == `OR1200_RST_VALUE)
|
sr_reg <= {2'h1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
|
sr_reg <= {2'b01, // Fixed one.
|
|
`OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
|
else if (except_started)
|
else if (except_started)
|
sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0];
|
sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0];
|
else if (sr_we)
|
else if (sr_we)
|
sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0];
|
sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0];
|
|
|
// EPH part of Supervision register
|
// EPH part of Supervision register
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
// default value
|
// default value
|
if (rst == `OR1200_RST_VALUE) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
sr_reg_bit_eph <= `OR1200_SR_EPH_DEF;
|
sr_reg_bit_eph <= `OR1200_SR_EPH_DEF;
|
sr_reg_bit_eph_select <= 1'b1; // select async. value due to reset state
|
// select async. value due to reset state
|
|
sr_reg_bit_eph_select <= 1'b1;
|
end
|
end
|
// selected value (different from default) is written into FF after reset state
|
// selected value (different from default) is written into FF after reset
|
|
// state
|
else if (sr_reg_bit_eph_select) begin
|
else if (sr_reg_bit_eph_select) begin
|
sr_reg_bit_eph <= boot_adr_sel_i; // dynamic value can only be assigned to FF out of reset!
|
// dynamic value can only be assigned to FF out of reset!
|
|
sr_reg_bit_eph <= boot_adr_sel_i;
|
sr_reg_bit_eph_select <= 1'b0; // select FF value
|
sr_reg_bit_eph_select <= 1'b0; // select FF value
|
end
|
end
|
else if (sr_we) begin
|
else if (sr_we) begin
|
sr_reg_bit_eph <= to_sr[`OR1200_SR_EPH];
|
sr_reg_bit_eph <= to_sr[`OR1200_SR_EPH];
|
end
|
end
|
|
|
// select async. value of EPH bit after reset
|
// select async. value of EPH bit after reset
|
assign sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ? boot_adr_sel_i : sr_reg_bit_eph;
|
assign sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ?
|
|
boot_adr_sel_i : sr_reg_bit_eph;
|
|
|
// EPH part joined together with rest of Supervision register
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// EPH part joined together with rest of Supervision register
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always @(sr_reg or sr_reg_bit_eph_muxed)
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always @(sr_reg or sr_reg_bit_eph_muxed)
|
sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed, sr_reg[`OR1200_SR_WIDTH-4:0]};
|
sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed,
|
|
sr_reg[`OR1200_SR_WIDTH-4:0]};
|
|
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`ifdef verilator
|
`ifdef verilator
|
// Function to access various sprs (for Verilator). Have to hide this from
|
// Function to access various sprs (for Verilator). Have to hide this from
|
// simulator, since functions with no inputs are not allowed in IEEE
|
// simulator, since functions with no inputs are not allowed in IEEE
|
// 1364-2001.
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// 1364-2001.
|
| Line 383... |
Line 441... |
get_esr = {{32-`OR1200_SR_WIDTH{1'b0}},esr};
|
get_esr = {{32-`OR1200_SR_WIDTH{1'b0}},esr};
|
endfunction // get_esr
|
endfunction // get_esr
|
|
|
`endif
|
`endif
|
|
|
|
|
//
|
//
|
// MTSPR/MFSPR interface
|
// MTSPR/MFSPR interface
|
//
|
//
|
always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
|
always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
|
spr_dat_fpu or
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spr_dat_fpu or
|
