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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_sprs.v] - Diff between revs 456 and 502

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Rev 456 Rev 502
Line 55... Line 55...
                   // Clk & Rst
                   // Clk & Rst
                   clk, rst,
                   clk, rst,
 
 
                   // Internal CPU interface
                   // Internal CPU interface
                   flagforw, flag_we, flag, cyforw, cy_we, carry,
                   flagforw, flag_we, flag, cyforw, cy_we, carry,
 
                   ovforw, ov_we,
                   addrbase, addrofs, dat_i, branch_op, ex_spr_read,
                   addrbase, addrofs, dat_i, branch_op, ex_spr_read,
                   ex_spr_write,
                   ex_spr_write,
                   epcr, eear, esr, except_started,
                   epcr, eear, esr, except_started,
                   to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
                   to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
                   spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc,
                   spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc,
Line 94... Line 95...
   input                                flag_we;        // From ALU
   input                                flag_we;        // From ALU
   output                               flag;           // SR[F]
   output                               flag;           // SR[F]
   input                                cyforw;         // From ALU
   input                                cyforw;         // From ALU
   input                                cy_we;          // From ALU
   input                                cy_we;          // From ALU
   output                               carry;          // SR[CY]
   output                               carry;          // SR[CY]
 
   input                                ovforw;         // From ALU
 
   input                                ov_we;          // From ALU
   input [width-1:0]                     addrbase;       // SPR base address
   input [width-1:0]                     addrbase;       // SPR base address
   input [15:0]                  addrofs;        // SPR offset
   input [15:0]                  addrofs;        // SPR offset
   input [width-1:0]                     dat_i;          // SPR write data
   input [width-1:0]                     dat_i;          // SPR write data
   input                                ex_spr_read;    // l.mfspr in EX
   input                                ex_spr_read;    // l.mfspr in EX
   input                                ex_spr_write;   // l.mtspr in EX
   input                                ex_spr_write;   // l.mtspr in EX
Line 283... Line 286...
   //
   //
 
 
   //
   //
   // What to write into SR
   // What to write into SR
   //
   //
   assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV]
   assign to_sr[`OR1200_SR_FO:`OR1200_SR_OVE]
            = (except_started) ? sr[`OR1200_SR_FO:`OR1200_SR_OV] :
            = (except_started) ? {sr[`OR1200_SR_FO:`OR1200_SR_DSX],1'b0} :
              (branch_op == `OR1200_BRANCHOP_RFE) ?
              (branch_op == `OR1200_BRANCHOP_RFE) ?
              esr[`OR1200_SR_FO:`OR1200_SR_OV] : (spr_we && sr_sel) ?
              esr[`OR1200_SR_FO:`OR1200_SR_OVE] : (spr_we && sr_sel) ?
              {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]} :
              {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OVE]} :
              sr[`OR1200_SR_FO:`OR1200_SR_OV];
              sr[`OR1200_SR_FO:`OR1200_SR_OVE];
   assign to_sr[`OR1200_SR_TED]
   assign to_sr[`OR1200_SR_TED]
            = (except_started) ? 1'b1 :
            = (except_started) ? 1'b1 :
              (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
              (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
              (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED] :
              (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED] :
              sr[`OR1200_SR_TED];
              sr[`OR1200_SR_TED];
 
   assign to_sr[`OR1200_SR_OV]
 
            = (except_started) ? sr[`OR1200_SR_OV] :
 
              (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_OV] :
 
              ov_we ? ovforw :
 
              (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_OV] :
 
              sr[`OR1200_SR_OV];
   assign to_sr[`OR1200_SR_CY]
   assign to_sr[`OR1200_SR_CY]
            = (except_started) ? sr[`OR1200_SR_CY] :
            = (except_started) ? sr[`OR1200_SR_CY] :
              (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
              (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
              cy_we ? cyforw :
              cy_we ? cyforw :
              (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
              (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
Line 343... Line 351...
 
 
   //
   //
   // Write enables for system SPRs
   // Write enables for system SPRs
   //
   //
   assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) |
   assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) |
                  flag_we | cy_we;
                  flag_we | cy_we | ov_we;
   assign pc_we = (du_write && (npc_sel | ppc_sel));
   assign pc_we = (du_write && (npc_sel | ppc_sel));
   assign epcr_we = (spr_we && epcr_sel);
   assign epcr_we = (spr_we && epcr_sel);
   assign eear_we = (spr_we && eear_sel);
   assign eear_we = (spr_we && eear_sel);
   assign esr_we = (spr_we && esr_sel);
   assign esr_we = (spr_we && esr_sel);
   assign fpcsr_we = (spr_we && fpcsr_sel);
   assign fpcsr_we = (spr_we && fpcsr_sel);

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