| Line 55... |
Line 55... |
// Clk & Rst
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// Clk & Rst
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clk, rst,
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clk, rst,
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// Internal CPU interface
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// Internal CPU interface
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flagforw, flag_we, flag, cyforw, cy_we, carry,
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flagforw, flag_we, flag, cyforw, cy_we, carry,
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ovforw, ov_we,
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addrbase, addrofs, dat_i, branch_op, ex_spr_read,
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addrbase, addrofs, dat_i, branch_op, ex_spr_read,
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ex_spr_write,
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ex_spr_write,
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epcr, eear, esr, except_started,
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epcr, eear, esr, except_started,
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to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
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to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
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spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc,
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spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc,
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| Line 94... |
Line 95... |
input flag_we; // From ALU
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input flag_we; // From ALU
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output flag; // SR[F]
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output flag; // SR[F]
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input cyforw; // From ALU
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input cyforw; // From ALU
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input cy_we; // From ALU
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input cy_we; // From ALU
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output carry; // SR[CY]
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output carry; // SR[CY]
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input ovforw; // From ALU
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input ov_we; // From ALU
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input [width-1:0] addrbase; // SPR base address
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input [width-1:0] addrbase; // SPR base address
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input [15:0] addrofs; // SPR offset
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input [15:0] addrofs; // SPR offset
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input [width-1:0] dat_i; // SPR write data
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input [width-1:0] dat_i; // SPR write data
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input ex_spr_read; // l.mfspr in EX
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input ex_spr_read; // l.mfspr in EX
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input ex_spr_write; // l.mtspr in EX
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input ex_spr_write; // l.mtspr in EX
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| Line 283... |
Line 286... |
//
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//
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//
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//
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// What to write into SR
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// What to write into SR
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//
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//
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assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV]
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assign to_sr[`OR1200_SR_FO:`OR1200_SR_OVE]
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= (except_started) ? sr[`OR1200_SR_FO:`OR1200_SR_OV] :
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= (except_started) ? {sr[`OR1200_SR_FO:`OR1200_SR_DSX],1'b0} :
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(branch_op == `OR1200_BRANCHOP_RFE) ?
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(branch_op == `OR1200_BRANCHOP_RFE) ?
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esr[`OR1200_SR_FO:`OR1200_SR_OV] : (spr_we && sr_sel) ?
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esr[`OR1200_SR_FO:`OR1200_SR_OVE] : (spr_we && sr_sel) ?
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{1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]} :
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{1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OVE]} :
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sr[`OR1200_SR_FO:`OR1200_SR_OV];
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sr[`OR1200_SR_FO:`OR1200_SR_OVE];
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assign to_sr[`OR1200_SR_TED]
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assign to_sr[`OR1200_SR_TED]
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= (except_started) ? 1'b1 :
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= (except_started) ? 1'b1 :
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
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(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED] :
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(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED] :
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sr[`OR1200_SR_TED];
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sr[`OR1200_SR_TED];
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assign to_sr[`OR1200_SR_OV]
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= (except_started) ? sr[`OR1200_SR_OV] :
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_OV] :
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ov_we ? ovforw :
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(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_OV] :
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sr[`OR1200_SR_OV];
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assign to_sr[`OR1200_SR_CY]
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assign to_sr[`OR1200_SR_CY]
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= (except_started) ? sr[`OR1200_SR_CY] :
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= (except_started) ? sr[`OR1200_SR_CY] :
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
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cy_we ? cyforw :
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cy_we ? cyforw :
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(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
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(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
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| Line 343... |
Line 351... |
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//
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//
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// Write enables for system SPRs
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// Write enables for system SPRs
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//
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//
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assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) |
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assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) |
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flag_we | cy_we;
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flag_we | cy_we | ov_we;
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assign pc_we = (du_write && (npc_sel | ppc_sel));
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assign pc_we = (du_write && (npc_sel | ppc_sel));
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assign epcr_we = (spr_we && epcr_sel);
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assign epcr_we = (spr_we && epcr_sel);
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assign eear_we = (spr_we && eear_sel);
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assign eear_we = (spr_we && eear_sel);
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assign esr_we = (spr_we && esr_sel);
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assign esr_we = (spr_we && esr_sel);
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assign fpcsr_we = (spr_we && fpcsr_sel);
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assign fpcsr_we = (spr_we && fpcsr_sel);
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