| Line 77... |
Line 77... |
biu_dat_o, biu_ack_o, biu_err_o
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biu_dat_o, biu_ack_o, biu_err_o
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter bl = 4; /* Can currently be either 4 or 8 - the two optional line
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sizes for the OR1200. */
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//
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//
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// RISC clock, reset and clock control
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// RISC clock, reset and clock control
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//
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//
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input clk; // RISC clock
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input clk; // RISC clock
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| Line 151... |
Line 154... |
`else
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`else
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wire retry_cnt;
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wire retry_cnt;
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assign retry_cnt = 1'b0;
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assign retry_cnt = 1'b0;
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`endif
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`endif
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`ifdef OR1200_WB_B3
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`ifdef OR1200_WB_B3
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reg [1:0] burst_len; // burst counter
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reg [3:0] burst_len; // burst counter
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`endif
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`endif
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reg biu_stb_reg; // WB strobe
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reg biu_stb_reg; // WB strobe
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wire biu_stb; // WB strobe
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wire biu_stb; // WB strobe
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reg wb_cyc_nxt; // next WB cycle value
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reg wb_cyc_nxt; // next WB cycle value
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| Line 195... |
Line 198... |
//
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//
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// WB burst tength counter
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// WB burst tength counter
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//
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//
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always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
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always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
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if (wb_rst_i == `OR1200_RST_VALUE) begin
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if (wb_rst_i == `OR1200_RST_VALUE) begin
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burst_len <= 2'h0;
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burst_len <= 0;
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end
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end
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else begin
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else begin
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// burst counter
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// burst counter
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if (wb_fsm_state_cur == wb_fsm_idle)
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if (wb_fsm_state_cur == wb_fsm_idle)
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burst_len <= 2'h2;
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burst_len <= bl[3:0] - 2;
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else if (wb_stb_o & wb_ack)
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else if (wb_stb_o & wb_ack)
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burst_len <= burst_len - 1'b1;
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burst_len <= burst_len - 1;
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end
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end
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end
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end
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//
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//
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// WB FSM - combinatorial part
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// WB FSM - combinatorial part
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| Line 231... |
Line 234... |
wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
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wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
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!(wb_ack & wb_cti_o == 3'b111);
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!(wb_ack & wb_cti_o == 3'b111);
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wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & !wb_ack |
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wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & !wb_ack |
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!wb_err_i & !wb_rty_i & wb_cti_o == 3'b010 /*& !wb_we_o -- Removed to add burst write, JPB*/;
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!wb_err_i & !wb_rty_i & wb_cti_o == 3'b010 /*& !wb_we_o -- Removed to add burst write, JPB*/;
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wb_cti_nxt[2] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[2];
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wb_cti_nxt[2] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[2];
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wb_cti_nxt[1] = 1'b1 ;
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wb_cti_nxt[1] = 1'b1 ;
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wb_cti_nxt[0] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[0];
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wb_cti_nxt[0] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[0];
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//if ((!biu_cyc_i | !biu_stb | !biu_cab_i) & wb_cti_o == 3'b010 |
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//if ((!biu_cyc_i | !biu_stb | !biu_cab_i) & wb_cti_o == 3'b010 |
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// biu_sel_i != wb_sel_o | biu_we_i != wb_we_o)
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// biu_sel_i != wb_sel_o | biu_we_i != wb_we_o)
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|
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if ((!biu_cyc_i | !biu_stb | !biu_cab_i | biu_sel_i != wb_sel_o |
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if ((!biu_cyc_i | !biu_stb | !biu_cab_i | biu_sel_i != wb_sel_o |
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biu_we_i != wb_we_o) & wb_cti_o == 3'b010)
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biu_we_i != wb_we_o) & wb_cti_o == 3'b010)
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| Line 280... |
Line 283... |
always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
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always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
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if (wb_rst_i == `OR1200_RST_VALUE) begin
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if (wb_rst_i == `OR1200_RST_VALUE) begin
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wb_cyc_o <= 1'b0;
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wb_cyc_o <= 1'b0;
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wb_stb_o <= 1'b0;
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wb_stb_o <= 1'b0;
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wb_cti_o <= 3'b111;
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wb_cti_o <= 3'b111;
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wb_bte_o <= 2'b01; // 4-beat wrap burst = constant
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wb_bte_o <= (bl==8) ? 2'b10 : (bl==4) ? 2'b01 : 2'b00;
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`ifdef OR1200_WB_CAB
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`ifdef OR1200_WB_CAB
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wb_cab_o <= 1'b0;
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wb_cab_o <= 1'b0;
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`endif
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`endif
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wb_we_o <= 1'b0;
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wb_we_o <= 1'b0;
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wb_sel_o <= 4'hf;
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wb_sel_o <= 4'hf;
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| Line 299... |
Line 302... |
if (wb_ack & wb_cti_o == 3'b111)
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if (wb_ack & wb_cti_o == 3'b111)
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wb_stb_o <= 1'b0;
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wb_stb_o <= 1'b0;
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else
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else
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wb_stb_o <= wb_stb_nxt;
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wb_stb_o <= wb_stb_nxt;
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wb_cti_o <= wb_cti_nxt;
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wb_cti_o <= wb_cti_nxt;
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wb_bte_o <= 2'b01; // 4-beat wrap burst = constant
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wb_bte_o <= (bl==8) ? 2'b10 : (bl==4) ? 2'b01 : 2'b00;
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`ifdef OR1200_WB_CAB
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`ifdef OR1200_WB_CAB
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wb_cab_o <= biu_cab_i;
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wb_cab_o <= biu_cab_i;
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`endif
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`endif
|
// we and sel - set at beginning of access
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// we and sel - set at beginning of access
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if (wb_fsm_state_cur == wb_fsm_idle) begin
|
if (wb_fsm_state_cur == wb_fsm_idle) begin
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| Line 313... |
Line 316... |
// adr - set at beginning of access and changed at every termination
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// adr - set at beginning of access and changed at every termination
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if (wb_fsm_state_cur == wb_fsm_idle) begin
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if (wb_fsm_state_cur == wb_fsm_idle) begin
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wb_adr_o <= biu_adr_i;
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wb_adr_o <= biu_adr_i;
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end
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end
|
else if (wb_stb_o & wb_ack) begin
|
else if (wb_stb_o & wb_ack) begin
|
wb_adr_o[3:2] <= wb_adr_o[3:2] + 1'b1;
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if (bl==4) begin
|
|
wb_adr_o[3:2] <= wb_adr_o[3:2] + 1;
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|
end
|
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if (bl==8) begin
|
|
wb_adr_o[4:2] <= wb_adr_o[4:2] + 1;
|
|
end
|
end
|
end
|
`ifdef OR1200_NO_DC
|
`ifdef OR1200_NO_DC
|
// dat - write data changed after avery subsequent write access
|
// dat - write data changed after avery subsequent write access
|
if (!wb_stb_o) begin
|
if (!wb_stb_o) begin
|
wb_dat_o <= biu_dat_i;
|
wb_dat_o <= biu_dat_i;
|
