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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_wb_biu.v] - Diff between revs 363 and 477

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Rev 363 Rev 477
Line 77... Line 77...
                     biu_dat_o, biu_ack_o, biu_err_o
                     biu_dat_o, biu_ack_o, biu_err_o
                     );
                     );
 
 
   parameter dw = `OR1200_OPERAND_WIDTH;
   parameter dw = `OR1200_OPERAND_WIDTH;
   parameter aw = `OR1200_OPERAND_WIDTH;
   parameter aw = `OR1200_OPERAND_WIDTH;
 
   parameter bl = 4; /* Can currently be either 4 or 8 - the two optional line
 
                      sizes for the OR1200. */
 
 
 
 
   //
   //
   // RISC clock, reset and clock control
   // RISC clock, reset and clock control
   //
   //
   input                                clk;            // RISC clock
   input                                clk;            // RISC clock
Line 151... Line 154...
`else
`else
   wire                                 retry_cnt;
   wire                                 retry_cnt;
   assign retry_cnt = 1'b0;
   assign retry_cnt = 1'b0;
`endif
`endif
`ifdef OR1200_WB_B3
`ifdef OR1200_WB_B3
   reg [1:0]                             burst_len;      // burst counter
   reg [3:0]                             burst_len;      // burst counter
`endif
`endif
 
 
   reg                                  biu_stb_reg;    // WB strobe
   reg                                  biu_stb_reg;    // WB strobe
   wire                                 biu_stb;        // WB strobe
   wire                                 biu_stb;        // WB strobe
   reg                                  wb_cyc_nxt;     // next WB cycle value
   reg                                  wb_cyc_nxt;     // next WB cycle value
Line 195... Line 198...
   //
   //
   // WB burst tength counter
   // WB burst tength counter
   // 
   // 
   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
      if (wb_rst_i == `OR1200_RST_VALUE) begin
      if (wb_rst_i == `OR1200_RST_VALUE) begin
         burst_len <=  2'h0;
         burst_len <= 0;
      end
      end
      else begin
      else begin
         // burst counter
         // burst counter
         if (wb_fsm_state_cur == wb_fsm_idle)
         if (wb_fsm_state_cur == wb_fsm_idle)
           burst_len <=  2'h2;
           burst_len <=  bl[3:0] - 2;
         else if (wb_stb_o & wb_ack)
         else if (wb_stb_o & wb_ack)
           burst_len <=  burst_len - 1'b1;
           burst_len <=  burst_len - 1;
      end
      end
   end
   end
 
 
   // 
   // 
   // WB FSM - combinatorial part
   // WB FSM - combinatorial part
Line 231... Line 234...
           wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
           wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
                        !(wb_ack & wb_cti_o == 3'b111);
                        !(wb_ack & wb_cti_o == 3'b111);
 
 
           wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & !wb_ack |
           wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & !wb_ack |
                        !wb_err_i & !wb_rty_i & wb_cti_o == 3'b010 /*& !wb_we_o -- Removed to add burst write, JPB*/;
                        !wb_err_i & !wb_rty_i & wb_cti_o == 3'b010 /*& !wb_we_o -- Removed to add burst write, JPB*/;
 
 
           wb_cti_nxt[2] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[2];
           wb_cti_nxt[2] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[2];
           wb_cti_nxt[1] = 1'b1  ;
           wb_cti_nxt[1] = 1'b1  ;
           wb_cti_nxt[0] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[0];
           wb_cti_nxt[0] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[0];
 
 
 
 
           //if ((!biu_cyc_i | !biu_stb | !biu_cab_i) & wb_cti_o == 3'b010  | 
           //if ((!biu_cyc_i | !biu_stb | !biu_cab_i) & wb_cti_o == 3'b010  | 
           //     biu_sel_i != wb_sel_o | biu_we_i != wb_we_o)
           //     biu_sel_i != wb_sel_o | biu_we_i != wb_we_o)
 
 
           if ((!biu_cyc_i | !biu_stb | !biu_cab_i | biu_sel_i != wb_sel_o |
           if ((!biu_cyc_i | !biu_stb | !biu_cab_i | biu_sel_i != wb_sel_o |
                biu_we_i != wb_we_o) & wb_cti_o == 3'b010)
                biu_we_i != wb_we_o) & wb_cti_o == 3'b010)
Line 280... Line 283...
   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
      if (wb_rst_i == `OR1200_RST_VALUE) begin
      if (wb_rst_i == `OR1200_RST_VALUE) begin
         wb_cyc_o       <=  1'b0;
         wb_cyc_o       <=  1'b0;
         wb_stb_o       <=  1'b0;
         wb_stb_o       <=  1'b0;
         wb_cti_o       <=  3'b111;
         wb_cti_o       <=  3'b111;
         wb_bte_o       <=  2'b01;      // 4-beat wrap burst = constant
         wb_bte_o       <=  (bl==8) ? 2'b10 : (bl==4) ? 2'b01 : 2'b00;
`ifdef OR1200_WB_CAB
`ifdef OR1200_WB_CAB
         wb_cab_o       <=  1'b0;
         wb_cab_o       <=  1'b0;
`endif
`endif
         wb_we_o                <=  1'b0;
         wb_we_o                <=  1'b0;
         wb_sel_o       <=  4'hf;
         wb_sel_o       <=  4'hf;
Line 299... Line 302...
         if (wb_ack & wb_cti_o == 3'b111)
         if (wb_ack & wb_cti_o == 3'b111)
           wb_stb_o        <=  1'b0;
           wb_stb_o        <=  1'b0;
         else
         else
           wb_stb_o        <=  wb_stb_nxt;
           wb_stb_o        <=  wb_stb_nxt;
         wb_cti_o       <=  wb_cti_nxt;
         wb_cti_o       <=  wb_cti_nxt;
         wb_bte_o       <=  2'b01;      // 4-beat wrap burst = constant
         wb_bte_o       <=  (bl==8) ? 2'b10 : (bl==4) ? 2'b01 : 2'b00;
`ifdef OR1200_WB_CAB
`ifdef OR1200_WB_CAB
         wb_cab_o       <=  biu_cab_i;
         wb_cab_o       <=  biu_cab_i;
`endif
`endif
         // we and sel - set at beginning of access 
         // we and sel - set at beginning of access 
         if (wb_fsm_state_cur == wb_fsm_idle) begin
         if (wb_fsm_state_cur == wb_fsm_idle) begin
Line 313... Line 316...
         // adr - set at beginning of access and changed at every termination 
         // adr - set at beginning of access and changed at every termination 
         if (wb_fsm_state_cur == wb_fsm_idle) begin
         if (wb_fsm_state_cur == wb_fsm_idle) begin
            wb_adr_o    <=  biu_adr_i;
            wb_adr_o    <=  biu_adr_i;
         end
         end
         else if (wb_stb_o & wb_ack) begin
         else if (wb_stb_o & wb_ack) begin
            wb_adr_o[3:2]       <=  wb_adr_o[3:2] + 1'b1;
            if (bl==4) begin
 
               wb_adr_o[3:2]    <=  wb_adr_o[3:2] + 1;
 
            end
 
            if (bl==8) begin
 
               wb_adr_o[4:2]    <=  wb_adr_o[4:2] + 1;
 
            end
         end
         end
`ifdef OR1200_NO_DC
`ifdef OR1200_NO_DC
         // dat - write data changed after avery subsequent write access
         // dat - write data changed after avery subsequent write access
         if (!wb_stb_o) begin
         if (!wb_stb_o) begin
            wb_dat_o    <=  biu_dat_i;
            wb_dat_o    <=  biu_dat_i;

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