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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's WISHBONE BIU ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// Description ////
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//// Implements WISHBONE interface ////
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//// ////
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//// To Do: ////
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//// - if biu_cyc/stb are deasserted and wb_ack_i is asserted ////
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//// and this happens even before aborted_r is asssrted, ////
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//// wb_ack_i will be delivered even though transfer is ////
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//// internally considered already aborted. However most ////
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//// wb_ack_i are externally registered and delayed. Normally ////
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//// this shouldn't cause any problems. ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Log: or1200_wb_biu.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Structure reordered and bugs fixed.
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_wb_biu(
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// RISC clock, reset and clock control
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clk, rst, clmode,
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// WISHBONE interface
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wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
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wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,
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`ifdef OR1200_WB_CAB
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wb_cab_o,
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`endif
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`ifdef OR1200_WB_B3
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wb_cti_o, wb_bte_o,
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`endif
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// Internal RISC bus
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biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,
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biu_dat_o, biu_ack_o, biu_err_o
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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//
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// RISC clock, reset and clock control
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//
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input clk; // RISC clock
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input rst; // RISC reset
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input [1:0] clmode; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
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//
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// WISHBONE interface
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//
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input wb_clk_i; // clock input
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input wb_rst_i; // reset input
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input wb_ack_i; // normal termination
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input wb_err_i; // termination w/ error
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input wb_rty_i; // termination w/ retry
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input [dw-1:0] wb_dat_i; // input data bus
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output wb_cyc_o; // cycle valid output
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output [aw-1:0] wb_adr_o; // address bus outputs
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output wb_stb_o; // strobe output
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output wb_we_o; // indicates write transfer
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output [3:0] wb_sel_o; // byte select outputs
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output [dw-1:0] wb_dat_o; // output data bus
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`ifdef OR1200_WB_CAB
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output wb_cab_o; // consecutive address burst
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`endif
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`ifdef OR1200_WB_B3
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output [2:0] wb_cti_o; // cycle type identifier
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output [1:0] wb_bte_o; // burst type extension
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`endif
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//
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// Internal RISC interface
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//
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input [dw-1:0] biu_dat_i; // input data bus
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input [aw-1:0] biu_adr_i; // address bus
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input biu_cyc_i; // WB cycle
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input biu_stb_i; // WB strobe
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input biu_we_i; // WB write enable
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input biu_cab_i; // CAB input
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input [3:0] biu_sel_i; // byte selects
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output [31:0] biu_dat_o; // output data bus
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output biu_ack_o; // ack output
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output biu_err_o; // err output
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//
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// Registers
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//
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wire wb_ack; // normal termination
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reg [aw-1:0] wb_adr_o; // address bus outputs
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reg wb_cyc_o; // cycle output
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reg wb_stb_o; // strobe output
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reg wb_we_o; // indicates write transfer
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reg [3:0] wb_sel_o; // byte select outputs
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`ifdef OR1200_WB_CAB
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reg wb_cab_o; // CAB output
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`endif
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`ifdef OR1200_WB_B3
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reg [2:0] wb_cti_o; // cycle type identifier
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reg [1:0] wb_bte_o; // burst type extension
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`endif
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`ifdef OR1200_NO_DC
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reg [dw-1:0] wb_dat_o; // output data bus
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`else
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assign wb_dat_o = biu_dat_i; // No register on this - straight from DCRAM
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`endif
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`ifdef OR1200_WB_RETRY
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reg [`OR1200_WB_RETRY-1:0] retry_cnt; // Retry counter
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`else
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wire retry_cnt;
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assign retry_cnt = 1'b0;
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`endif
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`ifdef OR1200_WB_B3
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reg [1:0] burst_len; // burst counter
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`endif
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reg biu_stb_reg; // WB strobe
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wire biu_stb; // WB strobe
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reg wb_cyc_nxt; // next WB cycle value
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reg wb_stb_nxt; // next WB strobe value
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reg [2:0] wb_cti_nxt; // next cycle type identifier value
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reg wb_ack_cnt; // WB ack toggle counter
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reg wb_err_cnt; // WB err toggle counter
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reg wb_rty_cnt; // WB rty toggle counter
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reg biu_ack_cnt; // BIU ack toggle counter
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reg biu_err_cnt; // BIU err toggle counter
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reg biu_rty_cnt; // BIU rty toggle counter
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wire biu_rty; // BIU rty indicator
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reg [1:0] wb_fsm_state_cur; // WB FSM - surrent state
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reg [1:0] wb_fsm_state_nxt; // WB FSM - next state
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wire [1:0] wb_fsm_idle = 2'h0; // WB FSM state - IDLE
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wire [1:0] wb_fsm_trans = 2'h1; // WB FSM state - normal TRANSFER
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wire [1:0] wb_fsm_last = 2'h2; // EB FSM state - LAST transfer
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//
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// WISHBONE I/F <-> Internal RISC I/F conversion
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//
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//assign wb_ack = wb_ack_i;
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assign wb_ack = wb_ack_i & !wb_err_i & !wb_rty_i;
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//
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// WB FSM - register part
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//
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always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
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if (wb_rst_i == `OR1200_RST_VALUE)
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wb_fsm_state_cur <= wb_fsm_idle;
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else
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wb_fsm_state_cur <= wb_fsm_state_nxt;
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end
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//
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// WB burst tength counter
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//
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always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
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if (wb_rst_i == `OR1200_RST_VALUE) begin
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burst_len <= 2'h0;
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end
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else begin
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// burst counter
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if (wb_fsm_state_cur == wb_fsm_idle)
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burst_len <= 2'h2;
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else if (wb_stb_o & wb_ack)
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burst_len <= burst_len - 1'b1;
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end
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end
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//
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// WB FSM - combinatorial part
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//
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always @(wb_fsm_state_cur or burst_len or wb_err_i or wb_rty_i or wb_ack or
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wb_cti_o or wb_sel_o or wb_stb_o or wb_we_o or biu_cyc_i or
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biu_stb or biu_cab_i or biu_sel_i or biu_we_i) begin
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// States of WISHBONE Finite State Machine
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case(wb_fsm_state_cur)
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// IDLE
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wb_fsm_idle : begin
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wb_cyc_nxt = biu_cyc_i & biu_stb;
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wb_stb_nxt = biu_cyc_i & biu_stb;
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wb_cti_nxt = {!biu_cab_i, 1'b1, !biu_cab_i};
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if (biu_cyc_i & biu_stb)
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wb_fsm_state_nxt = wb_fsm_trans;
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else
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wb_fsm_state_nxt = wb_fsm_idle;
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end
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// normal TRANSFER
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wb_fsm_trans : begin
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wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
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!(wb_ack & wb_cti_o == 3'b111);
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wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & !wb_ack |
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!wb_err_i & !wb_rty_i & wb_cti_o == 3'b010 /*& !wb_we_o -- Removed to add burst write, JPB*/;
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wb_cti_nxt[2] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[2];
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wb_cti_nxt[1] = 1'b1 ;
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wb_cti_nxt[0] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[0];
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//if ((!biu_cyc_i | !biu_stb | !biu_cab_i) & wb_cti_o == 3'b010 |
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// biu_sel_i != wb_sel_o | biu_we_i != wb_we_o)
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if ((!biu_cyc_i | !biu_stb | !biu_cab_i | biu_sel_i != wb_sel_o |
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biu_we_i != wb_we_o) & wb_cti_o == 3'b010)
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wb_fsm_state_nxt = wb_fsm_last;
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else if ((wb_err_i | wb_rty_i | wb_ack & wb_cti_o==3'b111) &
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wb_stb_o)
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wb_fsm_state_nxt = wb_fsm_idle;
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else
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wb_fsm_state_nxt = wb_fsm_trans;
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end
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// LAST transfer
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wb_fsm_last : begin
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wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
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!(wb_ack & wb_cti_o == 3'b111);
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wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
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!(wb_ack & wb_cti_o == 3'b111);
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wb_cti_nxt[2] = wb_ack & wb_stb_o | wb_cti_o[2];
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wb_cti_nxt[1] = 1'b1 ;
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wb_cti_nxt[0] = wb_ack & wb_stb_o | wb_cti_o[0];
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if ((wb_err_i | wb_rty_i | wb_ack & wb_cti_o == 3'b111) & wb_stb_o)
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wb_fsm_state_nxt = wb_fsm_idle;
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else
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wb_fsm_state_nxt = wb_fsm_last;
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end
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// default state
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default:begin
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wb_cyc_nxt = 1'bx;
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wb_stb_nxt = 1'bx;
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wb_cti_nxt = 3'bxxx;
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wb_fsm_state_nxt = 2'bxx;
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end
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endcase
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end
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//
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// WB FSM - output signals
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//
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always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
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if (wb_rst_i == `OR1200_RST_VALUE) begin
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wb_cyc_o <= 1'b0;
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wb_stb_o <= 1'b0;
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wb_cti_o <= 3'b111;
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wb_bte_o <= 2'b01; // 4-beat wrap burst = constant
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`ifdef OR1200_WB_CAB
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wb_cab_o <= 1'b0;
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`endif
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wb_we_o <= 1'b0;
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wb_sel_o <= 4'hf;
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wb_adr_o <= {aw{1'b0}};
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`ifdef OR1200_NO_DC
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wb_dat_o <= {dw{1'b0}};
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`endif
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end
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else begin
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wb_cyc_o <= wb_cyc_nxt;
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// wb_stb_o <= wb_stb_nxt;
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if (wb_ack & wb_cti_o == 3'b111)
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wb_stb_o <= 1'b0;
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else
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wb_stb_o <= wb_stb_nxt;
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wb_cti_o <= wb_cti_nxt;
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wb_bte_o <= 2'b01; // 4-beat wrap burst = constant
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`ifdef OR1200_WB_CAB
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wb_cab_o <= biu_cab_i;
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`endif
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// we and sel - set at beginning of access
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if (wb_fsm_state_cur == wb_fsm_idle) begin
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wb_we_o <= biu_we_i;
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wb_sel_o <= biu_sel_i;
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end
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// adr - set at beginning of access and changed at every termination
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if (wb_fsm_state_cur == wb_fsm_idle) begin
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wb_adr_o <= biu_adr_i;
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end
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else if (wb_stb_o & wb_ack) begin
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wb_adr_o[3:2] <= wb_adr_o[3:2] + 1'b1;
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end
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`ifdef OR1200_NO_DC
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// dat - write data changed after avery subsequent write access
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if (!wb_stb_o) begin
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wb_dat_o <= biu_dat_i;
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end
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`endif
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end
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end
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//
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// WB & BIU termination toggle counters
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//
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always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
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if (wb_rst_i == `OR1200_RST_VALUE) begin
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wb_ack_cnt <= 1'b0;
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wb_err_cnt <= 1'b0;
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wb_rty_cnt <= 1'b0;
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end
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else begin
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// WB ack toggle counter
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if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
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wb_ack_cnt <= 1'b0;
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else if (wb_stb_o & wb_ack)
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wb_ack_cnt <= !wb_ack_cnt;
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// WB err toggle counter
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if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
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wb_err_cnt <= 1'b0;
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else if (wb_stb_o & wb_err_i)
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wb_err_cnt <= !wb_err_cnt;
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// WB rty toggle counter
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if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
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wb_rty_cnt <= 1'b0;
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else if (wb_stb_o & wb_rty_i)
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wb_rty_cnt <= !wb_rty_cnt;
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end
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end
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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if (rst == `OR1200_RST_VALUE) begin
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biu_stb_reg <= 1'b0;
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biu_ack_cnt <= 1'b0;
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biu_err_cnt <= 1'b0;
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biu_rty_cnt <= 1'b0;
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`ifdef OR1200_WB_RETRY
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retry_cnt <= {`OR1200_WB_RETRY{1'b0}};
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`endif
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end
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else begin
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// BIU strobe
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if (biu_stb_i & !biu_cab_i & biu_ack_o)
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biu_stb_reg <= 1'b0;
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else
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biu_stb_reg <= biu_stb_i;
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// BIU ack toggle counter
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if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
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biu_ack_cnt <= 1'b0 ;
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else if (biu_ack_o)
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biu_ack_cnt <= !biu_ack_cnt ;
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// BIU err toggle counter
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if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
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biu_err_cnt <= 1'b0 ;
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else if (wb_err_i & biu_err_o)
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biu_err_cnt <= !biu_err_cnt ;
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// BIU rty toggle counter
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if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
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biu_rty_cnt <= 1'b0 ;
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else if (biu_rty)
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biu_rty_cnt <= !biu_rty_cnt ;
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`ifdef OR1200_WB_RETRY
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if (biu_ack_o | biu_err_o)
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retry_cnt <= {`OR1200_WB_RETRY{1'b0}};
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else if (biu_rty)
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retry_cnt <= retry_cnt + 1'b1;
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`endif
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end
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end
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assign biu_stb = biu_stb_i & biu_stb_reg;
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//
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// Input BIU data bus
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//
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assign biu_dat_o = wb_dat_i;
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//
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// Input BIU termination signals
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//
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assign biu_rty = (wb_fsm_state_cur == wb_fsm_trans) & wb_rty_i & wb_stb_o & (wb_rty_cnt ~^ biu_rty_cnt);
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assign biu_ack_o = (wb_fsm_state_cur == wb_fsm_trans) & wb_ack & wb_stb_o & (wb_ack_cnt ~^ biu_ack_cnt);
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assign biu_err_o = (wb_fsm_state_cur == wb_fsm_trans) & wb_err_i & wb_stb_o & (wb_err_cnt ~^ biu_err_cnt)
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`ifdef OR1200_WB_RETRY
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| biu_rty & retry_cnt[`OR1200_WB_RETRY-1];
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`else
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;
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`endif
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endmodule
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No newline at end of file
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No newline at end of file
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