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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Xilinx Virtex RAM 32x8D ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// Description ////
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//// Virtex dual-port memory ////
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//// ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: or1200_xcv_ram32x8d.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// No update
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//
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// Revision 1.2 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.7 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.6 2001/10/14 13:12:10 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.1 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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`ifdef OR1200_XILINX_RAM32X1D
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`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D
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module or1200_xcv_ram32x8d
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(
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DPO,
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SPO,
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A,
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D,
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DPRA,
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WCLK,
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WE
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);
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output [7:0] DPO;
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output [7:0] SPO;
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input [4:0] A;
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input [4:0] DPRA;
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input [7:0] D;
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input WCLK;
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input WE;
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wire [7:0] DPO_0;
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wire [7:0] SPO_0;
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wire [7:0] DPO_1;
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wire [7:0] SPO_1;
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wire WE_0 ;
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wire WE_1 ;
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assign DPO = DPRA[4] ? DPO_1 : DPO_0 ;
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assign SPO = A[4] ? SPO_1 : SPO_0 ;
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assign WE_0 = !A[4] && WE ;
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assign WE_1 = A[4] && WE ;
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RAM16X1D ram32x1d_0_0(
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.DPO(DPO_0[0]),
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.SPO(SPO_0[0]),
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.A0(A[0]),
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.A1(A[1]),
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.A2(A[2]),
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.A3(A[3]),
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.D(D[0]),
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.DPRA0(DPRA[0]),
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.DPRA1(DPRA[1]),
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.DPRA2(DPRA[2]),
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.DPRA3(DPRA[3]),
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.WCLK(WCLK),
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.WE(WE_0)
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);
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//
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// Instantiation of block 1
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//
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RAM16X1D ram32x1d_0_1(
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.DPO(DPO_0[1]),
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.SPO(SPO_0[1]),
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.A0(A[0]),
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.A1(A[1]),
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.A2(A[2]),
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.A3(A[3]),
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.D(D[1]),
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.DPRA0(DPRA[0]),
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.DPRA1(DPRA[1]),
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.DPRA2(DPRA[2]),
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.DPRA3(DPRA[3]),
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.WCLK(WCLK),
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.WE(WE_0)
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);
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//
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// Instantiation of block 2
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//
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RAM16X1D ram32x1d_0_2(
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.DPO(DPO_0[2]),
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.SPO(SPO_0[2]),
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.A0(A[0]),
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.A1(A[1]),
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.A2(A[2]),
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.A3(A[3]),
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.D(D[2]),
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.DPRA0(DPRA[0]),
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.DPRA1(DPRA[1]),
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.DPRA2(DPRA[2]),
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.DPRA3(DPRA[3]),
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.WCLK(WCLK),
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.WE(WE_0)
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);
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//
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// Instantiation of block 3
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//
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RAM16X1D ram32x1d_0_3(
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.DPO(DPO_0[3]),
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.SPO(SPO_0[3]),
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.A0(A[0]),
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.A1(A[1]),
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.A2(A[2]),
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.A3(A[3]),
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.D(D[3]),
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.DPRA0(DPRA[0]),
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.DPRA1(DPRA[1]),
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.DPRA2(DPRA[2]),
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.DPRA3(DPRA[3]),
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.WCLK(WCLK),
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.WE(WE_0)
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);
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//
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// Instantiation of block 4
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//
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RAM16X1D ram32x1d_0_4(
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.DPO(DPO_0[4]),
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.SPO(SPO_0[4]),
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.A0(A[0]),
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.A1(A[1]),
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.A2(A[2]),
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.A3(A[3]),
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.D(D[4]),
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.DPRA0(DPRA[0]),
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.DPRA1(DPRA[1]),
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.DPRA2(DPRA[2]),
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.DPRA3(DPRA[3]),
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.WCLK(WCLK),
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.WE(WE_0)
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);
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//
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// Instantiation of block 5
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//
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RAM16X1D ram32x1d_0_5(
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.DPO(DPO_0[5]),
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.SPO(SPO_0[5]),
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.A0(A[0]),
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.A1(A[1]),
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.A2(A[2]),
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.A3(A[3]),
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.D(D[5]),
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.DPRA0(DPRA[0]),
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.DPRA1(DPRA[1]),
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.DPRA2(DPRA[2]),
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.DPRA3(DPRA[3]),
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.WCLK(WCLK),
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.WE(WE_0)
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);
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//
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// Instantiation of block 6
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//
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RAM16X1D ram32x1d_0_6(
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.DPO(DPO_0[6]),
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.SPO(SPO_0[6]),
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.A0(A[0]),
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.A1(A[1]),
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.A2(A[2]),
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.A3(A[3]),
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.D(D[6]),
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.DPRA0(DPRA[0]),
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.DPRA1(DPRA[1]),
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.DPRA2(DPRA[2]),
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.DPRA3(DPRA[3]),
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.WCLK(WCLK),
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.WE(WE_0)
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);
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//
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// Instantiation of block 7
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//
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RAM16X1D ram32x1d_0_7(
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.DPO(DPO_0[7]),
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.SPO(SPO_0[7]),
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.A0(A[0]),
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.A1(A[1]),
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.A2(A[2]),
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.A3(A[3]),
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.D(D[7]),
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.DPRA0(DPRA[0]),
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.DPRA1(DPRA[1]),
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.DPRA2(DPRA[2]),
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.DPRA3(DPRA[3]),
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.WCLK(WCLK),
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.WE(WE_0)
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);
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RAM16X1D ram32x1d_1_0(
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.DPO(DPO_1[0]),
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.SPO(SPO_1[0]),
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.A0(A[0]),
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.A1(A[1]),
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.A2(A[2]),
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.A3(A[3]),
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.D(D[0]),
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.DPRA0(DPRA[0]),
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.DPRA1(DPRA[1]),
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.DPRA2(DPRA[2]),
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.DPRA3(DPRA[3]),
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.WCLK(WCLK),
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.WE(WE_1)
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);
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//
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// Instantiation of block 1
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//
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RAM16X1D ram32x1d_1_1(
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.DPO(DPO_1[1]),
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.SPO(SPO_1[1]),
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.A0(A[0]),
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.A1(A[1]),
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.A2(A[2]),
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.A3(A[3]),
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.D(D[1]),
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.DPRA0(DPRA[0]),
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.DPRA1(DPRA[1]),
|
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.DPRA2(DPRA[2]),
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.DPRA3(DPRA[3]),
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.WCLK(WCLK),
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.WE(WE_1)
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);
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//
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// Instantiation of block 2
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//
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RAM16X1D ram32x1d_1_2(
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.DPO(DPO_1[2]),
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.SPO(SPO_1[2]),
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.A0(A[0]),
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.A1(A[1]),
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.A2(A[2]),
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.A3(A[3]),
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.D(D[2]),
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.DPRA0(DPRA[0]),
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.DPRA1(DPRA[1]),
|
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.DPRA2(DPRA[2]),
|
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.DPRA3(DPRA[3]),
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.WCLK(WCLK),
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.WE(WE_1)
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);
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//
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// Instantiation of block 3
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//
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RAM16X1D ram32x1d_1_3(
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.DPO(DPO_1[3]),
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.SPO(SPO_1[3]),
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.A0(A[0]),
|
|
.A1(A[1]),
|
|
.A2(A[2]),
|
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.A3(A[3]),
|
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.D(D[3]),
|
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.DPRA0(DPRA[0]),
|
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.DPRA1(DPRA[1]),
|
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.DPRA2(DPRA[2]),
|
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.DPRA3(DPRA[3]),
|
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.WCLK(WCLK),
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.WE(WE_1)
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);
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//
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// Instantiation of block 4
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//
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RAM16X1D ram32x1d_1_4(
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.DPO(DPO_1[4]),
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.SPO(SPO_1[4]),
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.A0(A[0]),
|
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.A1(A[1]),
|
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.A2(A[2]),
|
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.A3(A[3]),
|
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.D(D[4]),
|
|
.DPRA0(DPRA[0]),
|
|
.DPRA1(DPRA[1]),
|
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.DPRA2(DPRA[2]),
|
|
.DPRA3(DPRA[3]),
|
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.WCLK(WCLK),
|
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.WE(WE_1)
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);
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|
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//
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// Instantiation of block 5
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//
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RAM16X1D ram32x1d_1_5(
|
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.DPO(DPO_1[5]),
|
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.SPO(SPO_1[5]),
|
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.A0(A[0]),
|
|
.A1(A[1]),
|
|
.A2(A[2]),
|
|
.A3(A[3]),
|
|
.D(D[5]),
|
|
.DPRA0(DPRA[0]),
|
|
.DPRA1(DPRA[1]),
|
|
.DPRA2(DPRA[2]),
|
|
.DPRA3(DPRA[3]),
|
|
.WCLK(WCLK),
|
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.WE(WE_1)
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);
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|
|
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//
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// Instantiation of block 6
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//
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RAM16X1D ram32x1d_1_6(
|
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.DPO(DPO_1[6]),
|
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.SPO(SPO_1[6]),
|
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.A0(A[0]),
|
|
.A1(A[1]),
|
|
.A2(A[2]),
|
|
.A3(A[3]),
|
|
.D(D[6]),
|
|
.DPRA0(DPRA[0]),
|
|
.DPRA1(DPRA[1]),
|
|
.DPRA2(DPRA[2]),
|
|
.DPRA3(DPRA[3]),
|
|
.WCLK(WCLK),
|
|
.WE(WE_1)
|
|
);
|
|
|
|
//
|
|
// Instantiation of block 7
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//
|
|
RAM16X1D ram32x1d_1_7(
|
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.DPO(DPO_1[7]),
|
|
.SPO(SPO_1[7]),
|
|
.A0(A[0]),
|
|
.A1(A[1]),
|
|
.A2(A[2]),
|
|
.A3(A[3]),
|
|
.D(D[7]),
|
|
.DPRA0(DPRA[0]),
|
|
.DPRA1(DPRA[1]),
|
|
.DPRA2(DPRA[2]),
|
|
.DPRA3(DPRA[3]),
|
|
.WCLK(WCLK),
|
|
.WE(WE_1)
|
|
);
|
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endmodule
|
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|
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`else
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|
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module or1200_xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);
|
|
|
|
//
|
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// I/O
|
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//
|
|
output [7:0] DPO;
|
|
output [7:0] SPO;
|
|
input [4:0] A;
|
|
input [4:0] DPRA;
|
|
input [7:0] D;
|
|
input WCLK;
|
|
input WE;
|
|
|
|
//
|
|
// Instantiation of block 0
|
|
//
|
|
RAM32X1D ram32x1d_0(
|
|
.DPO(DPO[0]),
|
|
.SPO(SPO[0]),
|
|
.A0(A[0]),
|
|
.A1(A[1]),
|
|
.A2(A[2]),
|
|
.A3(A[3]),
|
|
.A4(A[4]),
|
|
.D(D[0]),
|
|
.DPRA0(DPRA[0]),
|
|
.DPRA1(DPRA[1]),
|
|
.DPRA2(DPRA[2]),
|
|
.DPRA3(DPRA[3]),
|
|
.DPRA4(DPRA[4]),
|
|
.WCLK(WCLK),
|
|
.WE(WE)
|
|
);
|
|
|
|
//
|
|
// Instantiation of block 1
|
|
//
|
|
RAM32X1D ram32x1d_1(
|
|
.DPO(DPO[1]),
|
|
.SPO(SPO[1]),
|
|
.A0(A[0]),
|
|
.A1(A[1]),
|
|
.A2(A[2]),
|
|
.A3(A[3]),
|
|
.A4(A[4]),
|
|
.D(D[1]),
|
|
.DPRA0(DPRA[0]),
|
|
.DPRA1(DPRA[1]),
|
|
.DPRA2(DPRA[2]),
|
|
.DPRA3(DPRA[3]),
|
|
.DPRA4(DPRA[4]),
|
|
.WCLK(WCLK),
|
|
.WE(WE)
|
|
);
|
|
|
|
//
|
|
// Instantiation of block 2
|
|
//
|
|
RAM32X1D ram32x1d_2(
|
|
.DPO(DPO[2]),
|
|
.SPO(SPO[2]),
|
|
.A0(A[0]),
|
|
.A1(A[1]),
|
|
.A2(A[2]),
|
|
.A3(A[3]),
|
|
.A4(A[4]),
|
|
.D(D[2]),
|
|
.DPRA0(DPRA[0]),
|
|
.DPRA1(DPRA[1]),
|
|
.DPRA2(DPRA[2]),
|
|
.DPRA3(DPRA[3]),
|
|
.DPRA4(DPRA[4]),
|
|
.WCLK(WCLK),
|
|
.WE(WE)
|
|
);
|
|
|
|
//
|
|
// Instantiation of block 3
|
|
//
|
|
RAM32X1D ram32x1d_3(
|
|
.DPO(DPO[3]),
|
|
.SPO(SPO[3]),
|
|
.A0(A[0]),
|
|
.A1(A[1]),
|
|
.A2(A[2]),
|
|
.A3(A[3]),
|
|
.A4(A[4]),
|
|
.D(D[3]),
|
|
.DPRA0(DPRA[0]),
|
|
.DPRA1(DPRA[1]),
|
|
.DPRA2(DPRA[2]),
|
|
.DPRA3(DPRA[3]),
|
|
.DPRA4(DPRA[4]),
|
|
.WCLK(WCLK),
|
|
.WE(WE)
|
|
);
|
|
|
|
//
|
|
// Instantiation of block 4
|
|
//
|
|
RAM32X1D ram32x1d_4(
|
|
.DPO(DPO[4]),
|
|
.SPO(SPO[4]),
|
|
.A0(A[0]),
|
|
.A1(A[1]),
|
|
.A2(A[2]),
|
|
.A3(A[3]),
|
|
.A4(A[4]),
|
|
.D(D[4]),
|
|
.DPRA0(DPRA[0]),
|
|
.DPRA1(DPRA[1]),
|
|
.DPRA2(DPRA[2]),
|
|
.DPRA3(DPRA[3]),
|
|
.DPRA4(DPRA[4]),
|
|
.WCLK(WCLK),
|
|
.WE(WE)
|
|
);
|
|
|
|
//
|
|
// Instantiation of block 5
|
|
//
|
|
RAM32X1D ram32x1d_5(
|
|
.DPO(DPO[5]),
|
|
.SPO(SPO[5]),
|
|
.A0(A[0]),
|
|
.A1(A[1]),
|
|
.A2(A[2]),
|
|
.A3(A[3]),
|
|
.A4(A[4]),
|
|
.D(D[5]),
|
|
.DPRA0(DPRA[0]),
|
|
.DPRA1(DPRA[1]),
|
|
.DPRA2(DPRA[2]),
|
|
.DPRA3(DPRA[3]),
|
|
.DPRA4(DPRA[4]),
|
|
.WCLK(WCLK),
|
|
.WE(WE)
|
|
);
|
|
|
|
//
|
|
// Instantiation of block 6
|
|
//
|
|
RAM32X1D ram32x1d_6(
|
|
.DPO(DPO[6]),
|
|
.SPO(SPO[6]),
|
|
.A0(A[0]),
|
|
.A1(A[1]),
|
|
.A2(A[2]),
|
|
.A3(A[3]),
|
|
.A4(A[4]),
|
|
.D(D[6]),
|
|
.DPRA0(DPRA[0]),
|
|
.DPRA1(DPRA[1]),
|
|
.DPRA2(DPRA[2]),
|
|
.DPRA3(DPRA[3]),
|
|
.DPRA4(DPRA[4]),
|
|
.WCLK(WCLK),
|
|
.WE(WE)
|
|
);
|
|
|
|
//
|
|
// Instantiation of block 7
|
|
//
|
|
RAM32X1D ram32x1d_7(
|
|
.DPO(DPO[7]),
|
|
.SPO(SPO[7]),
|
|
.A0(A[0]),
|
|
.A1(A[1]),
|
|
.A2(A[2]),
|
|
.A3(A[3]),
|
|
.A4(A[4]),
|
|
.D(D[7]),
|
|
.DPRA0(DPRA[0]),
|
|
.DPRA1(DPRA[1]),
|
|
.DPRA2(DPRA[2]),
|
|
.DPRA3(DPRA[3]),
|
|
.DPRA4(DPRA[4]),
|
|
.WCLK(WCLK),
|
|
.WE(WE)
|
|
);
|
|
|
|
endmodule
|
|
`endif
|
|
`endif
|
|
|
No newline at end of file
|
No newline at end of file
|
