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module ram_wb ( dat_i, dat_o, adr_i, we_i, sel_i, cyc_i, stb_i, ack_o, cti_i, clk_i, rst_i);
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module ram_wb
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(
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// Inputs
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wbm0_adr_i, wbm0_bte_i, wbm0_cti_i, wbm0_cyc_i, wbm0_dat_i, wbm0_sel_i,
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wbm0_stb_i, wbm0_we_i,
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// Outputs
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wbm0_ack_o, wbm0_err_o, wbm0_rty_o, wbm0_dat_o,
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// Inputs
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wbm1_adr_i, wbm1_bte_i, wbm1_cti_i, wbm1_cyc_i, wbm1_dat_i, wbm1_sel_i,
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wbm1_stb_i, wbm1_we_i,
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// Outputs
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wbm1_ack_o, wbm1_err_o, wbm1_rty_o, wbm1_dat_o,
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parameter dat_width = 32;
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// Clock, reset
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parameter adr_width = 12;
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wb_clk_i, wb_rst_i
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parameter mem_size = 262144; // Default is 1MB (262144 32-bit words)
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);
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// Bus parameters
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// wishbone signals
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parameter dw = 32;
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input [31:0] dat_i;
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parameter aw = 32;
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output [31:0] dat_o;
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// Memory parameters
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input [adr_width-1:2] adr_i;
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parameter mem_span = 32'h0000_0400;
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input we_i;
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parameter adr_width_for_span = 11; //(log2(mem_span));
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input [3:0] sel_i;
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input cyc_i;
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input stb_i;
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input [aw-1:0] wbm0_adr_i;
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output reg ack_o;
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input [1:0] wbm0_bte_i;
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input [2:0] cti_i;
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input [2:0] wbm0_cti_i;
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input wbm0_cyc_i;
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// clock
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input [dw-1:0] wbm0_dat_i;
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input clk_i;
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input [3:0] wbm0_sel_i;
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// async reset
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input wbm0_stb_i;
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input rst_i;
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input wbm0_we_i;
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wire [31:0] wr_data;
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output wbm0_ack_o;
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output wbm0_err_o;
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// mux for data to ram
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output wbm0_rty_o;
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assign wr_data[31:24] = sel_i[3] ? dat_i[31:24] : dat_o[31:24];
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output [dw-1:0] wbm0_dat_o;
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assign wr_data[23:16] = sel_i[2] ? dat_i[23:16] : dat_o[23:16];
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assign wr_data[15: 8] = sel_i[1] ? dat_i[15: 8] : dat_o[15: 8];
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input [aw-1:0] wbm1_adr_i;
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assign wr_data[ 7: 0] = sel_i[0] ? dat_i[ 7: 0] : dat_o[ 7: 0];
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input [1:0] wbm1_bte_i;
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input [2:0] wbm1_cti_i;
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input wbm1_cyc_i;
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input [dw-1:0] wbm1_dat_i;
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input [3:0] wbm1_sel_i;
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input wbm1_stb_i;
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input wbm1_we_i;
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output wbm1_ack_o;
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output wbm1_err_o;
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output wbm1_rty_o;
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output [dw-1:0] wbm1_dat_o;
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input wb_clk_i;
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input wb_rst_i;
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// Internal wires to actual RAM
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wire [aw-1:0] wb_ram_adr_i;
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wire [1:0] wb_ram_bte_i;
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wire [2:0] wb_ram_cti_i;
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wire wb_ram_cyc_i;
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wire [dw-1:0] wb_ram_dat_i;
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wire [3:0] wb_ram_sel_i;
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wire wb_ram_stb_i;
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wire wb_ram_we_i;
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wire wb_ram_ack_o;
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wire wb_ram_err_o;
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wire wb_ram_rty_o;
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wire [dw-1:0] wb_ram_dat_o;
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reg [1:0] input_select, last_selected;
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wire arb_for_wbm0, arb_for_wbm1;
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// Wires allowing selection of new input
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assign arb_for_wbm0 = (last_selected[1] | !wbm1_cyc_i) & !(|input_select);
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assign arb_for_wbm1 = (last_selected[0] | !wbm0_cyc_i) & !(|input_select);
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// Master select logic
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always @(posedge wb_clk_i)
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if (wb_rst_i)
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input_select <= 0;
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else if ((input_select[0] & !wbm0_cyc_i) | (input_select[1] & !wbm1_cyc_i))
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input_select <= 0;
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else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
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input_select <= 2'b01;
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else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
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input_select <= 2'b10;
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always @(posedge wb_clk_i)
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if (wb_rst_i)
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last_selected <= 0;
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else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
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last_selected <= 2'b01;
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else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
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last_selected <= 2'b10;
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// Mux input signals to RAM (default to wbm0)
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assign wb_ram_adr_i = (input_select[1]) ? wbm1_adr_i :
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(input_select[0]) ? wbm0_adr_i : 0;
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assign wb_ram_bte_i = (input_select[1]) ? wbm1_bte_i :
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(input_select[0]) ? wbm0_bte_i : 0;
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assign wb_ram_cti_i = (input_select[1]) ? wbm1_cti_i :
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(input_select[0]) ? wbm0_cti_i : 0;
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assign wb_ram_cyc_i = (input_select[1]) ? wbm1_cyc_i :
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(input_select[0]) ? wbm0_cyc_i : 0;
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assign wb_ram_dat_i = (input_select[1]) ? wbm1_dat_i :
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(input_select[0]) ? wbm0_dat_i : 0;
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assign wb_ram_sel_i = (input_select[1]) ? wbm1_sel_i :
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(input_select[0]) ? wbm0_sel_i : 0;
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assign wb_ram_stb_i = (input_select[1]) ? wbm1_stb_i :
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(input_select[0]) ? wbm0_stb_i : 0;
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assign wb_ram_we_i = (input_select[1]) ? wbm1_we_i :
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(input_select[0]) ? wbm0_we_i : 0;
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// Output from RAM, gate the ACK, ERR, RTY signals appropriately
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assign wbm0_dat_o = wb_ram_dat_o;
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assign wbm0_ack_o = wb_ram_ack_o & input_select[0];
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assign wbm0_err_o = wb_ram_err_o & input_select[0];
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assign wbm0_rty_o = wb_ram_rty_o & input_select[0];
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assign wbm1_dat_o = wb_ram_dat_o;
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assign wbm1_ack_o = wb_ram_ack_o & input_select[1];
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assign wbm1_err_o = wb_ram_err_o & input_select[1];
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assign wbm1_rty_o = wb_ram_rty_o & input_select[1];
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ram_wb_sc_sw
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ram_wb_b3 ram_wb_b3_0
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#
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(
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(
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.dat_width(dat_width),
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// Outputs
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.adr_width(adr_width),
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.wb_ack_o (wb_ram_ack_o),
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.mem_size(mem_size)
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.wb_err_o (wb_ram_err_o),
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)
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.wb_rty_o (wb_ram_rty_o),
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ram0
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.wb_dat_o (wb_ram_dat_o),
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(
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// Inputs
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.dat_i(wr_data),
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.wb_adr_i (wb_ram_adr_i),
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.dat_o(dat_o),
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.wb_bte_i (wb_ram_bte_i),
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.adr_i({2'b00, adr_i}),
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.wb_cti_i (wb_ram_cti_i),
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.we_i(we_i & ack_o),
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.wb_cyc_i (wb_ram_cyc_i),
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.clk(clk_i)
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.wb_dat_i (wb_ram_dat_i),
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);
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.wb_sel_i (wb_ram_sel_i),
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.wb_stb_i (wb_ram_stb_i),
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.wb_we_i (wb_ram_we_i),
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.wb_clk_i (wb_clk_i),
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.wb_rst_i (wb_rst_i));
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defparam ram_wb_b3_0.aw = aw;
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defparam ram_wb_b3_0.dw = dw;
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defparam ram_wb_b3_0.mem_span = mem_span;
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defparam ram_wb_b3_0.adr_width_for_span = adr_width_for_span;
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// ack_o
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endmodule // ram_wb
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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ack_o <= 1'b0;
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else
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if (!ack_o)
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begin
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if (cyc_i & stb_i)
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ack_o <= 1'b1;
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end
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else
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ack_o <= 1'b0;
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// We did have acking logic which was sensitive to the
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// burst signals, cti_i, but this proved to cause problems
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// and we were never receiving back-to-back reads or writes
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// anyway. This logic which only acks one transaction at a
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// time appears to work well, despite not supporting burst
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// transactions.
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endmodule
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